System, method, and apparatus for generating a ramp signal with a changing slope

Patent metadata

Field	Value
Publication number	US-10043844-B2
Application number	US-201615211936-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Jul 18, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A device for generating a ramp signal with a changing slope is disclosed. The device may comprise a processor configured to generate a variable signal. The device may also comprise a phase-locked loop (PLL) circuit configured to receive the variable signal and a reference clock signal, generate a changing ramp clock signal based on the variable signal and the reference clock signal, and output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.

First claim

What is claimed is:

1. A device for generating a ramp signal with a changing slope, the device comprising:
a processor configured to generate a variable signal; and
a phase-locked loop (PLL) circuit configured to:
receive the variable signal and a reference clock signal,
generate a changing ramp clock signal based on the variable signal and the reference clock signal, and
output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.

2. The device of claim 1 , wherein:
the PLL circuit comprises a charge-pump with a low pass filter (CP-LPF); and
the CP-LPF is pre-configured to determine a loop bandwidth of the PLL, the loop bandwidth determining a lock time of the PLL.

3. The device of claim 2 , wherein the PLL is a fractional PLL including a Sigma-Delta modulator.

4. The device of claim 2 , wherein the PLL is an integer PLL.

5. The device of claim 1 , wherein the variable signal monotonically increases in value, causing the generated changing ramp clock signal to have a positive rate of increase.

6. The device of claim 5 , wherein:
the PLL circuit and the ADC circuit are components of a sensor; and
the sensor further comprises a photodiode array.

7. The device of claim 6 , wherein the ADC circuit comprises:
a ramp generator configured to convert the generated changing ramp clock signal to a changing ramp voltage signal;
one or more comparators each configured to:
receive the ramp voltage signal and a photodiode signal from a photodiode of the photodiode array,
compare the ramp voltage signal with the photodiode signal, and
switch if the ramp voltage signal exceeds the photodiode signal; and

one or more counters one-to-one corresponding to the one or more parallel comparators and configured to record a time from the ramp voltage signal starts in a cycle to a corresponding comparator switches.

8. The device of claim 7 , wherein the ramp generator includes at least one of a switch-capacitor based ramp generator, a current steering DAC based ramp generator, or a charge scaling DAC based ramp generator.

9. The device of claim 7 , wherein the one or more counters receive the generated changing ramp clock signal as a clock signal of the one or more counters, causing the ADC circuit to keep a same total ramping time per cycle with an increased bit range of the ADC circuit.

10. The device of claim 7 , wherein the one or more counters receive a constant external clock signal as a clock signal of the one or more counters, causing the ADC circuit to extend its dynamic range.

11. The device of claim 7 , further comprising a multiplexer (MUX) configured to:
receive the generated changing ramp clock signal and a constant external clock signal; and
select one of the generated changing ramp clock signal and the constant external clock signal as a clock signal of the one or more counters.

12. The device of claim 7 , wherein:
the generated changing ramp clock signal is cyclic;
at a beginning of each cycle corresponding to a first photodiode signal, the generated changing ramp clock signal has a first rate of change;
at an end of each cycle corresponding to a second photodiode signal, the generated changing ramp clock signal has a second rate of change;
the second photodiode signal is larger than the first photodiode signal; and
the second rate of change is larger than the first rate of change.

13. A method for generating a ramp signal with a changing slope, the method comprising:
generating, by a processor, a variable signal;
receiving, by a phase-locked loop (PLL) circuit, the variable signal and a reference clock signal;
generating, by the PLL circuit, a changing ramp clock signal based on the variable signal and the reference clock signal; and
outputting, by the PLL circuit, the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.

14. The method of claim 13 , wherein the PLL circuit comprises a charge-pump with a low pass filter (CP-LPF); and
further comprising pre-configuring the CP-LPF to determine a loop bandwidth of the PLL, the loop bandwidth determining a lock time of the PLL.

15. The method of claim 14 , wherein the PLL is a fractional PLL including a Sigma-Delta modulator.

16. The method of claim 14 , wherein the PLL is an integer PLL.

17. The method of claim 13 , wherein the variable pattern monotonically increases in value, causing the generated changing ramp clock signal to have a positive rate of increase.

18. The method of claim 17 , wherein:
the PLL circuit and the ADC circuit are components of a sensor; and
the sensor further comprises a photodiode array.

19. The method of claim 18 , further comprising:
converting, by a ramp generator of the ADC circuit, the generated changing ramp clock signal to a changing ramp voltage signal;
receiving, by one or more comparators of the ADC circuit, the ramp voltage signal and a photodiode signal from a photodiode of the photodiode array;
comparing, by the one or more comparators, the ramp voltage signal with the photodiode signal;
switching, by the one or more comparators, if the ramp voltage signal exceeds the photodiode signal; and
recording, by one or more counters of the ADC circuit, a time from the ramp voltage signal starts in a cycle to a corresponding comparator switches, the one or more counters one-to-one corresponding to the one or more parallel comparators.

20. The method of claim 19 , wherein the ramp generator includes at least one of a switch-capacitor based ramp generator, a current steering DAC based ramp generator, or a charge scaling DAC based ramp generator.

21. The method of claim 19 , wherein the one or more counters receive the generated changing ramp clock signal as a clock signal of the one or more counters, causing the ADC circuit to keep the same total ramping time per cycle with an increased bit range of the ADC circuit.

22. The method of claim 19 , wherein the one or more counters receive a constant external clock signal as a clock signal of the one or more counters, causing the ADC circuit to extend its dynamic range.

23. The method of claim 19 , further comprising:
receiving, by a multiplexer (MUX) of the ADC circuit, the generated changing ramp clock signal and a constant external clock signal; and
selecting, by the MUX, one of the generated changing ramp clock signal and the constant external clock signal as a clock signal of the one or more counters.

24. The method of claim 23 , wherein:
the generated changing ramp clock signal is cyclic;
at a beginning of each cycle corresponding to a first photodiode signal, the generated changing ramp clock signal has a first rate of change;
at an end of each cycle corresponding to a second photodiode signal, the generated changing ramp clock signal has a second rate of change;
the second photodiode signal is larger than the first photodiode signal; and
the second rate of change is larger than the first rate of change.

25. A sensor system for generating a ramp signal with a changing slope, comprising:
a photodiode array configured to convert a light signal to an electric signal;
a phase-locked loop (PLL) circuit configured to:
receive a variable signal and a reference clock signal, and
generate a changing ramp clock signal based on the variable signal and the reference clock signal; and

an analog-to-digital-converter (ADC) circuit configured t

Assignees

• Cista Sys Corp

Inventors

• Qiao Wenhao
• Zhang Guangbin
• Lee Dennis Tunglin

Classifications

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H03L7/18 Primary

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03K6/04

  Modifying slopes of pulses, e.g. S-correction (S-correction in television H04N3/23) · CPC title