Electrostatic protection device

Patent metadata

Field	Value
Publication number	US-10043792-B2
Application number	US-201615346527-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 4, 2009
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection device having mask-defined operational thresholds, wherein the ESD protection device comprises:
a p-type semiconductor region;
an n-type collector region positioned inside of the p-type semiconductor region;
a p-type base region positioned inside of the p-type semiconductor region and spaced apart from the n-type collector region, wherein the p-type base region has a higher doping concentration than the p-type semiconductor region;
an n-type emitter region positioned inside of the p-type semiconductor region and encircled by the p-type base region; and
a p-type buried region vertically positioned beneath the p-type base region and fully overlapping the p-type base region, wherein the p-type buried region has a higher doping concentration than the p-type semiconductor region,
wherein the n-type collector region, the p-type base region, and the n-type emitter region are configured to operate as a horizontal bipolar transistor, and wherein the p-type buried region inhibits formation of a vertical bipolar transistor.

2. The ESD protection device of claim 1 , wherein a horizontal spacing between the p-type base region and the n-type collector region establishes a trigger voltage at which the ESD protection device transitions from a non-conducting state to a conducting state.

3. The ESD protection device of claim 1 , wherein the n-type collector region is buried in the p-type semiconductor region, wherein at least a portion of the p-type buried region is horizontally aligned with the n-type collector region.

4. The ESD protection device of claim 3 , wherein a horizontal spacing between the p-type buried region and the n-type collector region establishes a trigger voltage at which the ESD protection device transitions from a non-conducting state to a conducting state.

5. The ESD protection device of claim 3 , wherein the p-type buried region and the p-type base region abut.

6. The ESD protection device of claim 1 , further comprising a base electrode connected to the p-type base region, an emitter electrode connected to the n-type emitter region, and a resistor electrically connected between the base electrode and the emitter electrode.

7. The ESD protection device of claim 1 , wherein the horizontal bipolar transistor is configured to turn on in response to an impact ionization current that forward biases a junction between the p-type base region and the n-type emitter region.

8. The ESD protection device of claim 1 , wherein a size of the p-type base region establishes a holding voltage of the ESD protection device.

9. The ESD protection device of claim 1 , wherein the p-type semiconductor region comprises a p-type well.

10. The ESD protection device of claim 9 , wherein the p-type base region and the p-type buried region are separated by a portion of the p-type well.

11. The ESD protection device of claim 1 , wherein the ESD protection device further comprises a field plate positioned over a portion of the p-type semiconductor region that is between the n-type collector region and the p-type base region.

12. The ESD protection device of claim 11 , wherein the field plate encircles the n-type emitter region.

13. The ESD protection device of claim 1 , further comprising an intrinsic region between the n-type emitter region and the p-type buried region.

14. The ESD protection device of claim 1 , wherein the n-type collector region encircles the p-type base region.

15. A method of forming an electrostatic discharge (ESD) protection device, the method comprising:
forming a horizontal bipolar transistor in a p-type semiconductor region, wherein forming the horizontal bipolar transistor comprises:
forming an n-type collector region inside of the p-type semiconductor region;
forming a p-type base region inside of the p-type semiconductor region and spaced apart from the n-type collector region, the p-type base region having a higher doping concentration than the p-type semiconductor region; and
forming an n-type emitter region inside of the p-type semiconductor region and encircled by the p-type base region; and

inhibiting formation of a vertical bipolar transistor by forming a p-type buried region vertically positioned beneath the p-type base region and fully overlapping the p-type base region, the p-type buried region having a higher doping concentration than the p-type semiconductor region.

16. An integrated circuit comprising:
a pin; and
a first electrostatic discharge (ESD) protection device comprising:
a p-type semiconductor region;
an n-type collector region positioned inside of the p-type semiconductor region;
a p-type base region positioned inside of the p-type semiconductor region and spaced apart from the n-type collector region, wherein the p-type base region has a higher doping concentration than the p-type semiconductor region;
an n-type emitter region positioned inside of the p-type semiconductor region and encircled by the p-type base region, wherein the n-type emitter region is electrically connected to the pin; and
a p-type buried region vertically positioned beneath the p-type base region and fully overlapping the p-type base region, wherein the p-type buried region has a higher doping concentration than the p-type semiconductor region,
wherein the n-type collector region, the p-type base region, and the n-type emitter region are configured to operate as a horizontal bipolar transistor, and
wherein the p-type buried region inhibits formation of a vertical bipolar transistor.

17. The integrated circuit of claim 16 , further comprising a substrate, wherein the p-type semiconductor region comprises a p-type well separated from the substrate by an insulating material.

18. The integrated circuit of claim 16 , further comprising a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a source region and a drain region, wherein the source region and the drain region share a common dopant dosage with the p-type base region.

19. The integrated circuit of claim 16 , further comprising a second ESD protection device comprising an n-type collector region electrically connected to the n-type collector region of the first ESD protection device, and an n-type emitter region electrically connected to ground.

20. The integrated circuit of claim 19 , wherein the first ESD protection device and the second ESD protection device are operable to provide bi-directional ESD protection.

21. The method of claim 15 , wherein a horizontal spacing between the p-type base region and the n-type collector region establishes a trigger voltage at which the ESD protection device transitions from a non-conducting state to a conducting state.

22. The method of claim 15 , further comprising burying the n-type collector region in the p-type semiconductor region such that at least a portion of the p-type buried region is horizontally aligned with the n-type collector region.

23. The method of claim 15 , wherein forming the p-type buried region comprises forming the p-type buried region to abut the p-type base region.

24. The method of claim 15 , further comprising:
forming a base electrode connected to the p-type base region;
forming an emitter region connected to the n-type emitter region; and
forming a resistor electrically connected between the base electrode and the emitter electrode.

25. The method of claim 15 , further comprising:
form

Assignees

• Analog Devices Inc

Inventors

• Coyne Edward John
• Mcguinness Patrick Martin
• Daly Paul Malachy
• Stenson Bernard Patrick
• Clarke David J
• Bain Andrew David
• Lane William Allan

Classifications

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L29/0821

  Electricity · mapped topic

• H01L29/735

  Electricity · mapped topic

• H01L29/402

  Electricity · mapped topic

• H01L29/6625

  Electricity · mapped topic