Integrated circuit packaging system and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-10043733-B1
Application number	US-201313844179-A
Country	US
Kind code	B1
Filing date	Mar 15, 2013
Priority date	Dec 9, 2008
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent.

First claim

What is claimed is:

1. An integrated circuit packaging system comprising:
a carrier;
a device mounted over the carrier, the device having an active side and an inactive side, wherein the active side includes an indent about a peripheral region of the active side, wherein the active side includes a flange about a perimeter of an elevated portion, the elevated portion about a central region of the active side, and wherein the device includes at least one of an integrated circuit, an interposer, and a laminated substrate;
a conformal interconnect, having an elevated segment, a sloped segment, and a flange segment, over the indent, wherein the sloped segment is between the flange segment and the elevated segment, and wherein the flange segment is connected to a first side of the carrier via internal interconnects, the internal interconnects including at least one solder bump or solder ball; and
an encapsulation over the device and the first side of the carrier exposing a second side of the carrier.

2. The system of claim 1 , wherein the active side includes a terminal pad, and wherein the elevated segment is over the terminal pad.

3. The system of claim 1 , wherein the active side includes a mounting pad, and wherein the mounting pad and the elevated segment are on the elevated portion of the active side.

4. The system of claim 1 , wherein the second side of the carrier includes external interconnects, the external interconnects including at least one of solder bump and solder ball.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Pagaila Reza Argenty
• Do Byung Tai
• Chua Linda Pei Ee

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/951

  Materials of bond pads · CPC title