Memory device and method of forming thereof

Patent metadata

Field	Value
Publication number	US-10043705-B2
Application number	US-201715423771-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Dec 5, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
forming a polish stop structure over a substrate having a metallization pattern thereon;
forming an opening in the polish stop structure to expose the metallization pattern;
overfilling the opening with a tungsten layer;
polishing a top surface of the tungsten layer until reaching the polish stop structure, wherein the polish stop structure has higher resistance to the polishing the top surface of the tungsten layer than that of the tungsten layer;
forming a bottom electrode layer over the polished tungsten layer, wherein forming the bottom electrode layer comprises:
forming a first conductive layer over the polished tungsten layer;
forming a second conductive layer over the first conductive layer; and
polishing the second conductive layer, wherein the first conductive layer has higher resistance to the polishing the second conductive layer than that of the second conductive layer; and
forming a resistance switching element over the bottom electrode layer.

2. The method of claim 1 , further comprising:
polishing the bottom electrode layer to leave a polished bottom electrode layer over the polished tungsten layer.

3. The method of claim 1 , further comprising:
forming a metal liner in the opening and over a top surface of the polish stop structure before the overfilling the opening with the tungsten layer, wherein the metal liner has higher resistance to the polishing the top surface of the tungsten layer than that of the tungsten layer.

4. The method of claim 1 , further comprising forming a diffusion barrier and a glue layer in the opening prior to overfilling the opening with the tungsten layer.

5. The method of claim 1 , wherein forming the polish stop structure comprises:
forming a first dielectric layer over the substrate; and
forming a second dielectric layer over the first dielectric layer.

6. A method of forming a memory device, comprising:
forming a stack of first and second dielectric layers over a metal structure;
forming a bottom electrode via (BEVA) structure penetrating through and over the stack of first and second dielectric layers, wherein forming the BEVA comprises forming a stack of a diffusion barrier layer, a glue layer and a tungsten layer, wherein the glue layer has higher adhesion to the tungsten layer than that of the diffusion barrier layer;
performing a first chemical mechanical polish (CMP) operation to the BEVA structure, wherein the first dielectric layer has higher polishing resistance to a slurry used in the first CMP operation than that of the second dielectric layer; and
forming a stack of a bottom electrode layer, a resistance switching layer and a top electrode layer over the BEVA structure.

7. The method of claim 6 , wherein the second dielectric layer has higher polishing resistance to the slurry used in the first CMP operation than that of the BEVA structure.

8. The method of claim 6 , wherein the forming the BEVA comprises forming a stack of a diffusion barrier layer and a tungsten layer, and the diffusion barrier layer has higher polishing resistance to the slurry used in the first CMP operation than that of the tungsten layer.

9. The method of claim 8 , wherein the second dielectric layer has higher polishing resistance to the slurry used in the first CMP operation than that of the diffusion barrier layer.

10. The method of claim 6 , wherein the forming the glue layer comprises forming in sequence a titanium layer and a titanium nitride layer.

11. The method of claim 6 , wherein the diffusion barrier layer is a tantalum nitride layer.

12. The method of claim 6 , wherein the forming the bottom electrode layer comprises:
forming a first metal layer over the BEVA structure and a second metal layer over the first metal layer; and
performing a second CMP operation to the second metal layer, wherein the first metal layer has higher polishing resistance to a slurry used in the second CMP operation than that of the second metal layer.

13. The method of claim 12 , wherein the slurry used in the first CMP operation and the slurry used in the second CMP operation are the same.

14. A method of forming a memory device, comprising:
forming a bottom electrode via (BEVA) structure in a dielectric structure and over a metal structure;
forming a stack of first and second conductive layers over the BEVA structure;
performing a first chemical mechanical polish (CMP) operation to the second conductive layer, wherein the first conductive layer has higher polishing resistance to a slurry used in the first CMP operation than that of the second conductive layer; and
forming a resistance switching layer and a top electrode layer over the second conductive layer.

15. The method of claim 14 , wherein the second conductive layer has higher oxidation resistance than that of the first conductive layer.

16. The method of claim 14 , wherein the second conductive layer is formed with a thickness greater than a thickness of the first conductive layer.

17. The method of claim 14 , wherein the forming the BEVA structure comprises:
forming in sequence a tantalum-containing layer, a titanium-containing layer and a tungsten layer.

18. The method of claim 17 , wherein the first conductive layer is formed in contact with the tantalum-containing layer, the titanium-containing layer and the tungsten layer of the BEVA structure.

19. The method of claim 14 , further comprising:
performing a second CMP operation to the BEVA structure prior to the forming the stack of first and second conductive layers, wherein a slurry used in the second CMP operation is the same as the slurry used in the first CMP operation.

20. The method of claim 19 , wherein the BEVA structure is formed with a void-free tungsten plug embedded in the dielectric structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Yen-Chang
• Chang Yao-Wen
• Chen Sheng-Chau
• Kalnitsky Alexander

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L21/7684

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic