Shift register and method for driving the same, driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10043586-B2
Application number	US-201615206391-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Mar 30, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A shift register includes a pulling-up unit, a pulling-down unit and an output unit, the pulling-up unit being connected to a first input terminal, a first clock signal terminal, a first level terminal, a pulling-down node and a pulling-up node, respectively, the pulling-down unit being connected to a second input terminal, a second level terminal, the first level terminal, the pulling-up node and the pulling-down node, respectively, and the output unit being connected to the first level terminal, a second clock signal terminal, an output terminal, the pulling-down node and the pulling-up node, respectively. The shift register provides an output signal through the output terminal according to the signals inputted from the first input terminal, the second input terminal, the first level terminal, the second level terminal, the first clock signal terminal and the second clock signal terminal.

First claim

What is claimed is:

1. A shift register, comprising:
a pulling-up unit, which is connected to a first input terminal, a first clock signal terminal, a first level terminal, a pulling-down node and a pulling-up node, respectively, and is configured to control a voltage level at the pulling-up node according to a voltage level at the pulling-down node and signals inputted from the first input terminal, the first level terminal and the first clock signal terminal;
a pulling-down unit, which is connected to a second input terminal, a second level terminal, the first level terminal, the pulling-down node and the pulling-up node, respectively, and is configured to control the voltage level at the pulling-down node according to the voltage level at the pulling-up node and signals inputted from the second input terminal, the second level terminal and the first level terminal; and
an output unit, which is connected to the first level terminal, a second clock signal terminal, an output terminal, the pulling-down node and the pulling-up node, respectively, and is configured to provide an output signal through the output terminal according to the voltage levels of the pulling-down node and the pulling-up node and signals inputted from the first level terminal and the second clock signal terminal.

2. The shift register according to claim 1 , wherein the output unit includes:
a first output module, which is connected to the first level terminal, the output terminal and the pulling-down node, respectively, and is configured to control the output signal outputted from the output terminal according to the signal inputted from the first level terminal and the voltage level at the pulling-up node; and
a second output module, which is connected to the second clock signal terminal, the output terminal and the pulling-up node, respectively, and is configured to control the output signal outputted from the output terminal according to the signal inputted from the second clock signal terminal and the voltage level at the pulling-up node.

3. The shift register according to claim 1 , wherein the pulling-up unit includes a first pulling-up transistor and a second pulling-up transistor;
a gate electrode of the first pulling-up transistor is connected to the pulling-down node, a first electrode of the first pulling-up transistor is connected to the first level terminal, and a second electrode of the first pulling-up transistor is connected to the pulling-up node; and
a gate electrode of the second pulling-up transistor is connected to the first clock signal terminal, a first electrode of the second pulling-up transistor is connected to the first input terminal, and a second electrode of the second pulling-up transistor is connected to the pulling-up node.

4. The shift register according to claim 1 , wherein the pulling-down unit includes a first pulling-down transistor and a second pulling-down transistor;
a gate electrode of the first pulling-down transistor is connected to the pulling-up node, a first electrode of the first pulling-down transistor is connected to the first level terminal, and a second electrode of the first pulling-down transistor is connected to the pulling-down node; and
a gate electrode of the second pulling-down transistor is connected to the second input terminal, a first electrode of the second pulling-down transistor is connected to the second level terminal, and a second electrode of the second pulling-down transistor is connected to the pulling-down node.

5. The shift register according to claim 2 , wherein the first output module includes an output transistor and a first capacitor;
a gate electrode of the output transistor is connected to the pulling-down node, a first electrode of the output transistor is connected to the first level terminal, and a second electrode of the output transistor is connected to the output terminal; and
a first end of the first capacitor is connected to the pulling-down node, and a second end of the first capacitor is connected to the first level terminal.

6. The shift register according to claim 2 , wherein the second output module includes an output transistor and a capacitor;
a gate electrode of the output transistor is connected to the pulling-up node, a first electrode of the output transistor is connected to the output terminal, and a second electrode of the output transistor is connected to the second clock signal terminal; and
a first end of the capacitor is connected to the pulling-up node, and a second end of the capacitor is connected to the output terminal.

7. A method for driving the shift register according to claim 1 , the first level terminal providing a high level, the second level terminal providing a low level, the method comprising steps of:
in a first stage, inputting a high-level signal from the first input terminal, inputting a low-level signal from the second input terminal, inputting a low-level signal from the first clock signal terminal, and inputting a high-level signal from the second clock signal terminal, such that the pulling-up node is driven to a high level by the pulling-up unit, the pulling-down node is driven to a low level by the pulling-down unit, and the output unit outputs a high-level signal from the output terminal of the shift register;
in a second stage, inputting a high-level signal from the first input terminal, inputting a low-level signal from the second input terminal, inputting a high-level signal from the first clock signal terminal, and inputting a low-level signal from the second clock signal terminal, such that the pulling-up node is driven to a high level by the pulling-up unit, the pulling-down node is driven to a low level by the pulling-down unit, and the output unit outputs a high-level signal from the output terminal of the shift register;
in a third stage, inputting a low-level signal from the first input terminal, inputting a high-level signal from the second input terminal, inputting a low-level signal from the first clock signal terminal, and inputting a high-level signal from the second clock signal terminal, such that the pulling-up node is driven to a low level by the pulling-up unit, the pulling-down node is driven to a high level by the pulling-down unit, and the output unit outputs a high-level signal from the output terminal of the shift register;
in a fourth stage, inputting a high-level signal from the first input terminal, inputting a high-level signal from the second input terminal, inputting a high-level signal from the first clock signal terminal, and inputting a low-level signal from the second clock signal terminal, such that the pulling-up node is driven to a low level by the pulling-up unit, the pulling-down node is driven to a high level by the pulling-down unit, and the output unit outputs a low-level signal from the output terminal of the shift register;
in a fifth stage, inputting a high-level signal from the first input terminal, inputting a low-level signal from the second input terminal, inputting a low-level signal from the first clock signal terminal, and inputting a high-level signal from the second clock signal terminal, such that the pulling-up node is driven to a high level by the pulling-up unit, the pulling-down node is driven to a low level by the pulling-down unit, and the output unit outputs a high-level signal from the output terminal of the shift register; and
in a sixth stage, inputting a high-level signal from the first input terminal, inputting a low-level signal from the second input terminal, inputting a high-level signal from the first clock signal terminal, and inputting a low-level signal from the second clock signal terminal, such that the pulling-up node is driven to a high level by the pulling-up unit, the pulling-down node is dr

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ma Zhanjie

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title