Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance

Patent metadata

Field	Value
Publication number	US-10043580-B2
Application number	US-201715790257-A
Country	US
Kind code	B2
Filing date	Oct 23, 2017
Priority date	Feb 28, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

First claim

What is claimed is:

1. A method of reading data from a nonvolatile memory device, the nonvolatile memory device including a plurality of cell strings, each cell string including a plurality of memory cells, at least two selection transistors disposed between the memory cells and a bit line, and at least two ground selection transistors disposed between the memory cells and a common source line wherein the memory cells, the string selection transistors, and the ground selection transistors are serially connected and stacked in a direction perpendicular to a substrate, the method comprising:
performing a preset operation, the preset operation comprising:
applying a first read voltage to a selected wordline;
applying a third read voltage to an unselected wordline;
applying a turn-on voltage to string selection transistors of a selected cell string;
applying the turn-on voltage to ground selection transistors of the selected cell string;
applying the turn-on voltage to string selection transistors of a unselected cell string; and
applying the turn-on voltage to at least one of the ground selection transistors of the unselected cell string; and

performing a read operation after performing the preset operation, the read operation comprising:
applying a second read voltage to the selected wordline;
applying the third read voltage to the unselected wordline;
applying the turn-on voltage to the string selection transistors of the selected cell string;
applying the turn-on voltage to the ground selection transistors of the selected cell string;
applying a turn-off voltage to the string selection transistors of the unselected cell string; and
applying the turn-off voltage to at least one of the ground selection transistors of the unselected cell string.

2. The method of claim 1 , where the level of the first read voltage is equal with the level of the second read voltage and lower than the level of the third read voltage.

3. The method of claim 1 , wherein the level of the first read voltage is higher than the level of the second read voltage and lower than the level of the third read voltage.

4. The method of claim 2 or 3 , wherein the level of the third read voltage is substantially equal with the level of the turn-on voltage.

5. The method of claim 1 , wherein the turn-on voltage is a power supply voltage.

6. The method of claim 1 , wherein the selected cell string and the unselected cell string are connected to the same bitline, the selected cell string being a cell sting including a selected memory cell and the unselected cell string being other than the selected cell string in a memory cell array.

7. The method of claim 6 , wherein the method further includes sensing data delivered to the bit line during the read operation with a sense amplifier.

8. The method of claim 7 , wherein the cell strings are arranged on the substrate in rows and columns, a row of cell strings is connected in common to a string selection line, and two or more rows of cell strings are connected in common to a ground selection line.

9. The method of claim 8 , wherein the turn-off voltage is a ground voltage.

10. A method of reading data from a nonvolatile memory device by performing a preset operation and a read operation sequentially, the nonvolatile memory device including a plurality of cell strings, each cell string including a plurality of memory cells, at least two selection transistors disposed between the memory cells and a bit line, and at least two ground selection transistors disposed between the memory cells and a common source line wherein the memory cells, the string selection transistors, and the ground selection transistors are serially connected and stacked in a direction perpendicular to a substrate, the method comprising:
applying a first turn-on voltage to string selection transistors of a selected cell string during the preset operation and the read operation;
applying a second turn-on voltage to one of ground selection transistors of the selected cell string during the preset operation and the read operation;
applying the first turn-on voltage to string selection transistors of a unselected cell string during the preset operation and thereafter, applying a turn-off voltage to the string selection transistors of the unselected cell string during the read operation; and
applying the second turn-on voltage to one of the ground selection transistors of the unselected cell string during the preset operation and thereafter, applying the turn-off voltage to one of the ground selection transistors of the unselected cell string during the read operation,
wherein the first turn-on voltage and the second turn-on voltage are different from each other.

11. The method of claim 10 , the method further including:
applying a first read voltage to a selected wordline during the preset operation and applying a second read voltage to the selected wordline during the read operation; and
applying a third read voltage to an unselected wordline during the preset operation and maintaining the third read voltage during the read operation,
wherein the level of the first read voltage is equal with the level of the second read voltage and lower than the level of the third read voltage.

12. The method of claim 10 , the method further including:
applying a first read voltage to a selected wordline during the preset operation and applying a second read voltage to the selected wordline during the read operation; and
applying a third read voltage to an unselected wordline during the preset operation and maintaining the third read voltage during the read operation,
wherein the level of the first read voltage is higher than the level of the second read voltage and lower than the level of the third read voltage.

13. The method of claim 11 or 12 , wherein the level of the third read voltage is substantially equal with the level of the first turn-on voltage.

14. The method of claim 10 , wherein the first turn-on voltage is power supply voltage.

15. The method of claim 14 , wherein the selected cell string and the unselected cell string are connected to the same bitline, the selected cell string being a cell sting including a selected memory cell and the unselected cell string being other than the selected cell string in a memory cell array.

16. The method of claim 15 , wherein the method further includes sensing data delivered to the bit line during the read operation with a sense amplifier.

17. The method of claim 16 , wherein the cell strings are arranged on the substrate in rows and columns, a row of cell strings is connected in common to a string selection line, and two or more rows of cell strings are connected in common to a ground selection line.

18. A method of reading data from a nonvolatile memory device by performing a preset operation and a read operation sequentially, the nonvolatile memory device including a plurality of cell strings, each cell string including a plurality of memory cells, at least two selection transistors disposed between the memory cells and a bit line, and at least two ground selection transistors disposed between the memory cells and a common source line wherein the memory cells, the string selection transistors, and the ground selection transistors are serially connected and stacked in a direction perpendicular to a substrate, the method comprising:
applying a first turn-on voltage to string selection transistors of a selected cell string during the preset operation and applying a second turn-on voltage to string selection transistors of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Jung Won-Taeck

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title