Display panel and electronic apparatus including the same

US10043453B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10043453-B2
Application numberUS-201715447743-A
CountryUS
Kind codeB2
Filing dateMar 2, 2017
Priority dateJun 17, 2016
Publication dateAug 7, 2018
Grant dateAug 7, 2018

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel including a substrate that includes a display region and a non-display region, the display region including a first and second display region spaced apart from each other, and the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first and second display region; a plurality of first pixels arranged on the first display region; a plurality of second pixels arranged on the second display region; a first and second voltage wiring on the non-display region to transmit a first and second driving voltage to the first and second pixel; and an auxiliary wiring extending in a second direction perpendicular to the first direction, on the intermediate non-display region, the auxiliary wiring crossing between the first and second display region, and being connected to one of the first and second voltage wiring.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a substrate that includes a display region and a non-display region defined therein, the display region including a first display region and a second display region spaced apart from each other in a first direction, and the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first display region and second display region; a plurality of first pixels arranged on the first display region; a plurality of second pixels arranged on the second display region; a first voltage wiring and a second voltage wiring on the non-display region to transmit a first driving voltage and a second driving voltage to the first pixel and the second pixel, respectively; and an auxiliary wiring extending in a second direction, which is perpendicular to the first direction, on the intermediate non-display region, the auxiliary wiring completely crossing between the first display region and the second display region, and being connected to one of the first voltage wiring and the second voltage wiring. 2. The display panel of claim 1 , wherein an interval between the first display region and the second display region is greater than a width of each of the first pixels and second pixels in the first direction. 3. The display panel of claim 1 , wherein a width of the auxiliary wiring in the first direction is greater than a width of each of the first pixels and second pixels in the first direction. 4. The display panel of claim 1 , wherein the first voltage wiring includes: a first portion directly connected to a first end of the auxiliary wiring on the edge non-display region and extending in the first direction; and a second portion directly connected to a second end of the auxiliary wiring on the edge non-display region and extending in the first direction. 5. The display panel of claim 1 , wherein the second voltage wiring includes: a first portion directly connected to a first end of the auxiliary wiring on the edge non-display region and extending in the first direction; and a second portion directly connected to a second end of the auxiliary wiring on the edge non-display region and extending in the first direction. 6. The display panel of claim 5 , wherein: the first voltage wiring includes a first portion and a second portion, the first portion and second portion completely crossing between the first display region and the second display region on the intermediate non-display region, and the first portion and second portion of the first voltage wiring have the auxiliary wiring therebetween, and each of the first portion and second portion extends parallel to the auxiliary wiring. 7. The display panel of claim 5 , wherein the first voltage wiring includes a first portion that extends in the second direction on the intermediate non-display region and completely crosses between the first display region and second display region, and overlaps the auxiliary wiring. 8. The display panel of claim 1 , further comprising: first gate lines each extending in the first direction on the first display region and each connected to first pixels on an identical row among the first pixels; second gate lines each extending in the first direction on the second display region and each connected to second pixels on an identical row among the second pixels; a first gate driving circuit between the first display region and the auxiliary wiring on the intermediate non-display region to drive the first gate lines; and a second gate driving circuit between the second display region and the auxiliary wiring on the intermediate non-display region to drive the second gate lines. 9. The display panel of claim 8 , further comprising a protection layer directly connected to the auxiliary wiring and covering the first gate driving circuit and second gate driving circuit on the intermediate non-display region. 10. The display panel of claim 1 , wherein: the substrate includes at least one transparent region within the intermediate non-display region, and the auxiliary wiring includes at least one opening corresponding to the at least one transparent region. 11. The display panel of claim 1 , further comprising: first voltage lines each extending in the second direction on the first display region and each connected to first pixels on an identical column among the first pixels; and second voltage lines each extending in the second direction on the second display region and each connected to second pixels on an identical column among the second pixels, wherein the first voltage wiring includes: a first portion directly connected to first ends of the first voltage lines on the edge non-display region and extending in the first direction; a second portion directly connected to second ends of the first voltage lines on the edge non-display region and extending in the first direction; a third portion directly connected to first ends of the second voltage lines on the edge non-display region and extending in the first direction; and a fourth portion directly connected to second ends of the second voltage lines on the edge non-display region and extending in the first direction. 12. The display panel of claim 1 , further comprising a common electrode directly connected to the second voltage wiring and entirely covering the first display region and second display region to apply the second driving voltage to the first pixels and second pixels. 13. The display panel of claim 1 , wherein: each of the first pixels and second pixels includes a light-emitting device and a pixel circuit that generates light-emission current flowing in the light-emitting device, the light-emitting device includes a pixel electrode, a common electrode to which the second driving voltage is applied, and an intermediate layer between the pixel electrode and the common electrode, and the pixel circuit is connected to the pixel electrode, the first driving voltage is applied to the pixel circuit, and the pixel circuit includes at least one thin film transistor. 14. The display panel of claim 13 , further comprising: an active layer on the substrate, the active layer including a source region, a channel region, and a drain region of the at least one thin film transistor; a first conductive layer on the substrate, the first conductive layer including a gate electrode of the at least one thin film transistor that overlaps the channel region; a second conductive layer on the first conductive layer, the second conductive layer including a connection electrode that connects one of the source region and the drain region to the pixel electrode; a third conductive layer on the second conductive layer, the third conductive layer including the pixel electrode; and a common electrode on the third conductive layer. 15. The display panel of claim 14 , wherein the auxiliary wiring includes an auxiliary wiring electrode of the second conductive layer. 16. The display panel of claim 14 , wherein the auxiliary wiring includes an auxiliary wiring electrode and a lower auxiliary wiring electrode of the first conductive layer, the lower auxiliary wiring electrode being connected to a lower part of the auxiliary wiring electrode. 17. The display panel of claim 14 , wherein the auxiliary wiring includes an auxiliary wiring electrode and an upper auxiliary wiring electrode of the third conductive layer, the upper auxiliary wiring electrode being connected to an upper part of the auxiliary wiring electrode.

Assignees

Inventors

Classifications

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • Layout of electrodes and connections · CPC title

  • in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • G09G3/3258Primary

    with pixel circuitry controlling the voltage across the light-emitting element · CPC title

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Frequently asked questions

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What does patent US10043453B2 cover?
A display panel including a substrate that includes a display region and a non-display region, the display region including a first and second display region spaced apart from each other, and the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first and second display region; a plurality of first pixels…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 07 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).