Sharing global route topologies in detailed routing

Patent metadata

Field	Value
Publication number	US-10042970-B2
Application number	US-201615191576-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.

First claim

What is claimed is:

1. A system for creating layouts of integrated circuits, the system comprising:
a memory storing computer readable instructions; and
a processor for executing the computer readable instructions to cause the system to perform:
accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit, the initial layout created by a global router based on the gate level design description, the initial layout of wires specifying connections between regions on the integrated circuit;
accessing a second layout that specifies, for each net, detailed routing information including connections between specific wires in the regions of the integrated circuit, the second layout created by a detailed router based on the initial layout and including a failing net that is missing a connection in the second layout between two of the regions;
generating a list of nets with a same source region and target region in the initial layout as the failing net;
selecting a net in the list of nets;
rerouting the failing net over the selected net, the rerouting comprising the global router updating the initial layout and the detailed router updating the second layout;
updating the congestion related metric for each net in response to the global router updating the initial layout; and
causing the integrated circuit to be fabricated based at least in part on the updated initial layout and the updated second layout.

2. The system of claim 1 , wherein the selecting comprises iterating through the list of nets in an order determined by the congestion related metrics until one of a net that corrects the failing net is identified and there are no more nets in the list of nets.

3. The system of claim 1 , wherein the instructions further cause the system to compute a congestion value for each pair of adjacent regions, wherein the congestion value is input to the selecting and the rerouting.

4. The system of claim 1 , wherein the instructions further cause the system to compute a weighted congestion score as the congestion metric for each net, the computing comprising:
computing a congestion value for each pair of adjacent regions that reflects a number of connections between the pair;
computing an average of the congestion values along a path of the net from source region to target region;
computing a maximum value of the congestion values along the path of the net from the source region to the target region; and
weighting the average and maximum congestion values along with an input weight of the net to generate the weighted congestion score for the net.

5. The system of claim 1 , wherein each net has two pin connections.

6. The system of claim 1 , wherein each net has at least three pin connections.

7. The system of claim 1 , wherein the instructions further cause the system to perform:
identifying a net which causes a design rule violation for the initial layout;
generating a second list of nets with the same source region and target region in the initial layout as the identified net;
selecting a second net in the second list of nets;
rerouting the identified net over the second selected net, the rerouting comprising the global router updating the initial layout; and
updating the congestion related metric for each net in response to rerouting the identified net over the second selected net.

8. The system of claim 7 , wherein the design rule violation is selected from the group consisting of a congestion violation, a length violation, and a timing violation.

9. A computer program for creating layouts of integrated circuits, the computer program product comprising:
a tangible storage medium readable by a processor and storing instructions executable by the processor for:
accessing, using a processor, an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit, the initial layout created by a global router based on the gate level design description, the initial layout of wires specifying connections between regions on the integrated circuit;
accessing, using the processor, a second layout that specifies, for each net, detailed routing information including connections between specific wires in the regions of the integrated circuit, the second layout created by a detailed router based on the initial layout and including a failing net that is missing a connection in the second layout between two of the regions;
generating a list of nets with a same source region and target region in the initial layout as the failing net;
selecting a net in the list of nets;
rerouting the failing net over the selected net, the rerouting comprising the global router updating the initial layout and the detailed router updating the second layout;
updating the congestion related metric for each net in response to the global router updating the initial layout; and
causing the integrated circuit to be fabricated based at least in part on the updated initial layout and the updated second layout.

10. The computer program product of claim 9 , wherein the selecting comprises iterating through the list of nets in an order based on the congestion related metrics until one of a net that corrects the failing net is identified and there are no more nets in the list of nets.

11. The computer program product of claim 9 , wherein the instructions are further executable for computing a congestion value for each pair of adjacent regions, wherein the congestion value is input to the selecting and the rerouting.

12. The computer program product of claim 9 , wherein the instructions are further executable for:
identifying a net which causes a design rule violation for the initial layout;
generating a second list of nets with the same source region and target region in the initial layout as the identified net;
selecting a second net in the second list of nets;
rerouting the identified net over the second selected net, the rerouting comprising the global router updating the initial layout; and
updating the congestion related metric for each net in response to rerouting the identified net over the second selected net.

Assignees

• IBM

Inventors

• Pandey Diwesh
• Peyer Sven

Classifications

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5081

  Physics · mapped topic