Apparatus and method for a scalable test engine

Patent metadata

Field	Value
Publication number	US-10042729-B2
Application number	US-201615089448-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

First claim

What is claimed is:

1. A scalable test engine comprising:
an input interface to receive commands and data from a processor core or an external test system, the commands and data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip;
a first circuit to establish communication with an IP block over a first interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and data, the IP block to process the test operations and generate results; and
a second circuit to receive the results from the IP block over the first interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis,
wherein the input interface comprises a sideband interface communicatively coupling the first and second circuits to the processor core.

2. The scalable test engine as in claim 1 wherein the first circuit includes a second interconnect fabric interface to communicatively couple the first circuit to the first interconnect fabric to which the IP block is also communicatively coupled.

3. The scalable test engine as in claim 2 wherein the first interconnect fabric comprises a primary scalable fabric (PSF) for interconnecting IP blocks within a semiconductor chip.

4. The scalable test engine as in claim 3 wherein the PSF comprises an Intel On-Chip System Fabric (IOSF).

5. The scalable test engine as in claim 2 wherein the first circuit is to implement a first finite state machine (FSM) to coordinate communication of the commands and data over the second interconnect fabric to the IP block.

6. The scalable test engine as in claim 5 wherein the first circuit further comprises:
a plurality of command/data buffers, one or more of the command/data buffers to store a particular type of command/data received over the input interface.

7. The scalable test engine as in claim 6 wherein a first command/data buffer is to store posted commands/data, a second command/data buffer is to store non-posted commands/data, and a third command/data buffer is to store completed commands/data.

8. The scalable test engine as in claim 5 further comprising a data generation circuit to generate data to be transmitted to the IP block in combination with a command from one of the command/data buffers under control by the first FSM.

9. The scalable test engine as in claim 1 wherein the results comprise one or more signatures generated at the IP block responsive to execution of the test operations, the IP block to transmit the one or more signatures to the second circuit over the first interconnect fabric.

10. The scalable test engine as in claim 9 wherein the signatures are to be compared against known good signatures to determine whether the IP block has passed the test operations.

11. The scalable test engine as in claim 1 wherein the first interconnect fabric is communicatively coupled to a memory controller to establish communication between a system memory and the first and second circuits.

12. The scalable test engine as in claim 1 further comprising:
an on-chip test access port (TAP) to implement a stateful protocol in accordance with a Joint Test Action Group (JTAG) standard.

13. The scalable test engine as in claim 1 wherein the second circuit comprises a plurality of multi-input serial registers (MISRs) to be updated with the results under control of a target finite state machine (FSM).

14. The scalable test engine as in claim 1 wherein the first circuit does not require a test wrapper to be built around the IP block.

15. A system-on-a-chip (SoC) comprising:
a plurality of intellectual property (IP) blocks interconnected on first interconnect fabric;
at least one processor core to execute instructions and process data;
an input interface to receive commands and data from the processor core or an external test system, the commands and data to specify one or more test operations to be performed on one or more IP blocks of a chip;
a first circuit to establish communication with an IP block over the first interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and data, the IP block to process the test operations and generate results; and
a second circuit to receive the results from the IP block over the first interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis,
wherein the input interface comprises a sideband interface communicatively coupling the first and second circuits to the processor core.

16. The SoC as in claim 15 wherein the first circuit includes a second interconnect fabric interface to communicatively couple the first circuit to the first interconnect fabric to which the IP block is also communicatively coupled.

17. The SoC as in claim 16 wherein the first interconnect fabric comprises a primary scalable fabric (PSF) for interconnecting IP blocks within a semiconductor chip.

18. The SoC as in claim 17 wherein the PSF comprises an Intel On-Chip System Fabric (IOSF).

19. The SoC as in claim 16 wherein the first circuit is to implement a first finite state machine (FSM) to coordinate communication of the commands and data over the second interconnect fabric to the IP block.

20. The SoC as in claim 19 wherein the first circuit further comprises:
a plurality of command/data buffers, one or more of the command/data buffers to store a particular type of command/data received over the input interface.

21. The SoC as in claim 20 wherein a first command/data buffer is to store posted commands/data, a second command/data buffer is to store non-posted commands/data, and a third command/data buffer is to store completed commands/data.

22. The SoC as in claim 19 further comprising a data generation circuit to generate data to be transmitted to the IP block in combination with a command from one of the command/data buffers under control by the first FSM.

23. The SoC as in claim 15 wherein the results comprise one or more signatures generated at the IP block responsive to execution of the test operations, the IP block to transmit the one or more signatures to the second circuit over the first interconnect fabric.

24. The SoC as in claim 23 wherein the signatures are to be compared against known good signatures to determine whether the IP block has passed the test operations.

25. The SoC as in claim 15 wherein the first interconnect fabric is communicatively coupled to a memory controller to establish communication between a system memory and the first and second circuits.

Assignees

• Pappu Lakshminarayana
• De Gruijl Robert
• Bhatt Suketu U
• Adler Robert P
• Gopal R Selvakumar Raja
• Tanadi Rius
• Intel Corp

Inventors

• Pappu Lakshminarayana
• De Gruijl Robert
• Bhatt Suketu U
• Adler Robert P
• Gopal R Selvakumar Raja
• Tanadi Rius

Classifications

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F11/2736 Primary

  using a dedicated service processor for test · CPC title

• G01R31/31915

  In-circuit Testers · CPC title