Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US10042694B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10042694-B2 |
| Application number | US-201615257347-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 6, 2016 |
| Priority date | Sep 6, 2016 |
| Publication date | Aug 7, 2018 |
| Grant date | Aug 7, 2018 |
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A method for validating control blocks in memory includes monitoring for operations configured to obtain storage space in memory. The method examines the storage space that has been obtained to identify control blocks stored in the storage space. These control blocks are then analyzed to determine whether the control blocks are valid. In certain embodiments, this may be accomplished by comparing the content of the control blocks to information in a validation table that indicates possible values and ranges of values for fields in the control blocks. If a control block is valid, the method records a date and time when the control block was validated. If a control block is not valid, the method generates a message indicating that the control block is not valid. A corresponding system and computer program product are also disclosed.
Opening claim text (preview).
The invention claimed is: 1. A method for validating control blocks in memory, the method comprising: monitoring for operations configured to obtain storage space in memory; examining the storage space that has been obtained to identify control blocks stored in the storage space; analyzing the control blocks to determine whether the control blocks are valid; if a control block is valid, recording a date and time when the control block was determined to be valid; and if a control block is not valid, generating a message indicating that the control block is not valid. 2. The method of claim 1 , wherein analyzing the control blocks comprises comparing content of the control blocks to information in a validation table, the information indicating at least one of possible values and ranges of values for fields in the control blocks. 3. The method of claim 1 , wherein analyzing the control blocks further comprises validating other control blocks that are referenced by the control blocks. 4. The method of claim 1 , wherein analyzing the control blocks further comprises validating chains of control blocks to which the control blocks belong. 5. The method of claim 1 , further comprising indicating, in the message, a date and time the control block was previously determined to be valid. 6. The method of claim 1 , further comprising monitoring for operations configured to release storage space from the memory. 7. The method of claim 6 , further comprising ceasing to examine the storage space that has been released. 8. A computer program product for validating control blocks in memory, the computer program product comprising a computer-readable storage medium having computer-usable program code embodied therein, the computer-usable program code comprising: computer-usable program code to monitor for operations configured to obtain storage space in memory; computer-usable program code to examine the storage space that has been obtained to identify control blocks stored in the storage space; computer-usable program code to analyze the control blocks to determine whether the control blocks are valid; computer-usable program code to, if a control block is valid, record a date and time when the control block was determined to be valid; and computer-usable program code to, if a control block is not valid, generate a message indicating that the control block is not valid. 9. The computer program product of claim 8 , wherein analyzing the control blocks comprises comparing content of the control blocks to information in a validation table, the information indicating at least one of possible values and ranges of values for fields in the control blocks. 10. The computer program product of claim 8 , wherein analyzing the control blocks further comprises validating other control blocks that are referenced by the control blocks. 11. The computer program product of claim 8 , wherein analyzing the control blocks further comprises validating chains of control blocks to which the control blocks belong. 12. The computer program product of claim 8 , further comprising computer-usable program code to indicate, in the message, a date and time the control block was previously determined to be valid. 13. The computer program product of claim 8 , further comprising computer-usable program code to monitor for operations configured to release storage space from the memory. 14. The computer program product of claim 13 , further comprising computer-usable program code to cease to examine the storage space that has been released. 15. A system for validating control blocks in memory, the system comprising: at least one processor; at least one memory device operably coupled to the at least one processor and storing instructions for execution on the at least one processor, the instructions causing the at least one processor to: monitor for operations configured to obtain storage space in memory; examine the storage space that has been obtained to identify control blocks stored in the storage space; analyze the control blocks to determine whether the control blocks are valid; if a control block is valid, record a date and time when the control block was determined to be valid; and if a control block is not valid, generate a message indicating that the control block is not valid. 16. The system of claim 15 , wherein analyzing the control blocks comprises comparing content of the control blocks to information in a validation table, the information indicating at least one of possible values and ranges of values for fields in the control blocks. 17. The system of claim 15 , wherein analyzing the control blocks further comprises validating other control blocks that are referenced by the control blocks. 18. The system of claim 15 , wherein analyzing the control blocks further comprises validating chains of control blocks to which the control blocks belong. 19. The system of claim 15 , wherein the instructions further cause the at least one processor to indicate, in the message, a date and time the control block was previously determined to be valid. 20. The system of claim 15 , wherein the instructions further cause the at least one processor to monitor for operations configured to release storage space from the memory, and cease to examine the storage space that has been released.
in relation to data integrity, e.g. data losses, bit errors · CPC title
Monitoring storage devices or systems · CPC title
Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title
in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title
Plurality of storage devices · CPC title
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