Method and storage array for processing a write data request

Patent metadata

Field	Value
Publication number	US-10042560-B2
Application number	US-201715449027-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Sep 15, 2014
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.

First claim

What is claimed is:

1. A method for processing a write data request in a storage array comprising an input/output manager, a switching device, a first controller, and a first cache device, and wherein the input/output manager, the first controller and the first cache device are coupled to the switching device, and the switching device is coupled to a storage unit in the storage array; the method comprising:
sending, by the input/output manager, a write data request to the first controller via the switching device;
obtaining, by the first controller for the write data request, a first cache address in the first cache device for storing data of the write data request;
sending, by the first controller, an identifier of the first cache device and the first cache address to the input/output manager, via the switching device; and
writing, by the input/output manager, the data of the write data request to the first cache address via the switching device according to the identifier of the first cache device and the first cache address.

2. The method according to claim 1 , wherein the write data request includes an address of the data; and the method further comprises:
receiving, by the input/output manager, a response sent by the first cache device, indicating that the data is written successfully;
sending a notification to the first controller from the input/output manager via the switching device, that the data is written to the first cache address; and
establishing by the first controller, according to the notification, a correspondence among the address of the data, the identifier of the first cache device, and the first cache address.

3. The method according to claim 1 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device, and the method further comprises:
obtaining, by the first controller for the write data request, a second cache address from the second cache device for storing the data;
sending, by the first controller, an identifier of the second cache device and the second cache address to the input/output manager, via the switching device; and
writing, by the input/output manager, the data to the second cache address via the switching device, according to the identifier of the second cache device and the second cache address.

4. The method according to claim 1 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device, the method further comprising:
obtaining, by the first controller for the write data request, a second cache address from the second cache device for storing the data;
sending, by the first controller, a write data instruction to the first cache device via the switching device, wherein the write data instruction includes an identifier of the second cache device and the second cache address; and
writing, by the first cache device, according to the write data instruction, the data to the second cache address, via the switching device.

5. The method according to claim 1 , wherein the write data request includes an address of the data, wherein the address of the data comprises an identifier of a target logical unit (LU) in which the data is located, a logical block address of the data, and a length of the data; and the method further comprising:
querying, by the input/output manager, according to the identifier of the target LU, a homing relationship between the target LU and the first controller that is stored in the input/output manager, and identifying that the first controller is a home controller of the target LU; and
sending, by the input/output manager, the write data request to the first controller via the switching device.

6. The method according to claim 1 , wherein the write data request includes an address of the data, wherein the address of the data comprises an identifier of a target logical unit (LU) in which the data is located, a logical block address of the data, and a length of the data; the storage array further including a second controller, wherein the second controller is coupled to the switching device; the method further comprising:
sending, by the input/output manager, the write data request to the second controller via the switching device;
determining, by the second controller according to the identifier of the target LU, that the first controller is a home controller of the target LU; and
sending, by the second controller, the write data request to the first controller via the switching device.

7. A storage array, including an input/output manager, a switching device, a first controller, and a first cache device, wherein the input/output manager, the first controller, and the first cache device are coupled to the switching device; and the switching device is coupled to a storage unit in the storage array;
the input/output manager is configured to send a write data request to the first controller via the switching device;
the first controller is configured to obtain, a first cache address in the first cache device for storing data of the write data request, for the write data request, and send an identifier of the first cache device and the first cache address to the input/output manager via the switching device; and
the input/output manager is further configured to write the data to the first cache address via the switching device according to the identifier of the first cache device and the first cache address.

8. The storage array according to claim 7 , wherein the write data request includes an address of the data;
the input/output manager is further configured to receive from the first cache device, a response indicating that the data is written successfully, and send a notification to the first controller, via the switching device, that the data is written to the first cache address; and
the first controller is further configured to establish a correspondence among the address of the data, the identifier of the first cache device, and the first cache address, according to the notification.

9. The storage array according to claim 7 , wherein the storage array further comprises a second cache device, wherein the second cache device is coupled to the switching device;
the first controller is further configured to obtain, for the write data request, a second cache address from the second cache device for storing the data, and send an identifier of the second cache device and the second cache address to the input/output manager via the switching device; and
the input/output manager is further configured to write the data to the second cache address via the switching device, according to the identifier of the second cache device and the second cache address.

10. The storage array according to claim 7 , wherein the first controller is further configured to obtain a second cache address from the second cache device for storing the data for the write data request, and send a write data instruction to the first cache device via the switching device, wherein the write data instruction includes an identifier of the second cache device and the second cache address; and
the first cache device is configured to write the data to the second cache address via the switching device, according to the write data instruction.

11. The storage array according to claim 7 , wherein the write data request includes an address of the data, wherein the address of the data comprises an identifier of a target logical unit (LU) in which the data is located, a logical block address of the data, and a length of the data; and the input/output manager is further configured to query a homing relationshi

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhang Wei
• Lu Xianhong
• Wei Mingchang
• Zhang Chenyi

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F2212/604

  Details relating to cache allocation · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F13/1668

  Details of memory controller · CPC title