Method and system for programming a multi-layer non-volatile memory having a single fold data path

Patent metadata

Field	Value
Publication number	US-10042553-B2
Application number	US-201514928582-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

First claim

We claim:

1. A method of managing data comprising:
performing, in a non-volatile memory system having a non-volatile memory with a plurality of layers and a controller in communication with the non-volatile memory, each of the plurality of layers having a different bit-per-cell data capacity, the following steps:
only directing data received from a host to a first layer of the plurality of layers;
only maintaining a single open block at a time in a second layer of the plurality of layers for receiving any data from the first layer;
prior to programming the data received from the host into the first layer, determining whether a maintenance operation is necessary for both the first layer and the second layer; and
in response to determining that the maintenance operation is necessary for both the first layer and the second layer,
selecting a maintenance cycle type from a predetermined set of maintenance cycle types for the non-volatile memory based on a status of the first layer and the second layer; and
when the selected maintenance cycle type includes instructions to transfer data from the first layer to the second layer and a relocation maintenance operation for relocating data from a source block into another block in the second layer:
executing the selected maintenance cycle type by:
 transferring valid data from the first layer to the single open block in the second layer via a single data path, wherein the non-volatile memory system only assigns a new open block in the second layer for receiving data from the first layer after the single open block is fully programmed; and
 transferring valid data from a selected relocation source block in the second layer to at least one intermediate destination block in the first layer for subsequent copying back to the second layer via the single data path.

2. The method of claim 1 , wherein determining that the maintenance operation is necessary comprises determining that an amount of free space in the first layer is less than a predetermined maintenance threshold.

3. The method of claim 2 , wherein the status of the first layer comprises an amount of valid data in the first layer, and wherein selecting the maintenance cycle type comprises selecting a maintenance cycle type that includes instructions to transfer data from the first layer to the second layer when the amount of valid data in the first layer is greater than or equal to a data transfer threshold.

4. The method of claim 3 , wherein the selected maintenance cycle type comprises a combination of instructions for programming data received from the host into the first layer and transferring data from at least one source block in the first layer to the single open block in the second layer.

5. The method of claim 4 , further comprising determining an interleave ratio for interleaving the programming of data received from the host and transferring data from the at least one source block, prior to executing the selected maintenance cycle, based on an amount of valid data in the at least one source block.

6. The method of claim 1 , wherein the first layer comprises a lower bit-per-cell-capacity than the second layer and wherein transferring valid data from the first layer to the single open block in the second layer comprises transferring the valid data from the first layer to the single open block via an on-chip copy process.

7. A memory system, comprising:
at least one non-volatile memory having a first layer and a second layer of non-volatile memory cells, wherein the first layer has only non-volatile memory cells configured at a first bit-per-cell capacity and the second layer has only non-volatile memory cells configured at a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and
data management circuitry in communication with the at least one non-volatile memory, wherein the data management circuitry comprises:
data flow path circuitry defining a plurality of predetermined data paths for programming data received from a host or maintenance operation data into the first layer, and defining only a single data path for programming any data into the second layer;
maintenance manager circuitry configured to:
select a foreground maintenance schedule to free space in at least one of the first and second layers based on a status of at least one of the first and second layers;
maintain no more than one open block at a time in the second layer for receiving data into the second layer; and
for a relocation maintenance operation in the second layer, copy valid data to at least one intermediate relocation block in the first layer before copying the valid data via the single data path into a current open block in the second layer;
and

program interleaving circuitry configured to interleave programming of data received from the host with maintenance operation writes for the foreground maintenance schedule selected by the maintenance manager circuitry along one or more data paths defined by the data flow path circuitry.

8. The memory system of claim 7 , wherein the single data path for programming any data into the second layer comprises a data path between the first layer and the second layer.

9. The memory system of claim 8 , wherein the single data path comprises an on-chip copy data path configured to copy data from the first layer to the second layer, wherein the data management circuitry is configured to only permit programming of data to the second layer via the single data path.

10. The memory system of claim 7 , wherein the first layer comprises a plurality of open blocks of memory cells, each of the plurality of open blocks being configured to receive data of a different data type from the host.

11. The memory system of claim 10 , wherein the first layer further comprises at least one open maintenance data block configured to only receive valid data relocated from a closed block in the first layer, and at least one open maintenance block configured to only receive valid data relocated from the second layer.

12. The memory system of claim 11 , wherein the plurality of open blocks comprises a random host data update block and a sequential host data update block.

13. The memory system of claim 7 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming a monolithic three-dimensional structure, wherein at least one portion of the memory cells is vertically disposed with respect to the silicon substrate.

14. The memory system of claim 7 , wherein the at least one non-volatile memory comprises a plurality of non-volatile memory die, and wherein the data management circuitry is configured to first select an available non-volatile memory die for programming data received from the host prior to selecting the foreground maintenance schedule.

15. A memory system, comprising:
at least one non-volatile memory having a first layer and a second layer of non-volatile memory cells, wherein the first layer has only non-volatile memory cells configured at a first bit-per-cell capacity and the second layer has only non-volatile memory cells configured at a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and
controller means, in communication with the at least one non-volatile memory, for:
identifying a type of data received from a host and determine whether a maintenance operation is necessary in the first layer before programming the received data;
selecting a maintenance cycle type from a predetermined set of maintenance cycle types for the non-volatile memory based on a status of the first layer;
when the

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Parker Liam Michael
• Bennett Alan David
• Sinclair Alan Welsh
• Gorobets Sergey Anatolievich

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F3/064

  Management of blocks · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G06F3/0688 Primary

  Non-volatile semiconductor memory arrays · CPC title

• G11C16/10

  Programming or data input circuits · CPC title