Liquid crystal display panel, array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10042211-B2
Application number	US-201514890677-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Sep 30, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

The disclosure provides a liquid crystal display panel, an array substrate and a manufacturing method thereof. In the method, controllable resistance spacer layers are formed on at least one of a source doped region and a drain doped region of a low temperature polysilicon active layer, wherein when a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current, and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current, such that a contact region formed of the controllable resistance spacer layers is connected the corresponding source layer and the corresponding drain through the controllable resistance spacer layers. Therefore, the disclosure is capable of effectively decreasing a leakage of a thin film transistor.

First claim

What is claimed is:

1. An array substrate, comprising: a low temperature polysilicon active layer, a gate layer, an inter layer dielectric layer, a source layer and a drain layer formed on a substrate; wherein the inter layer dielectric layer is disposed on the low temperature polysilicon active layer, the source layer and the drain layer is disposed on the inter layer dielectric layer, and the gate layer is disposed on the low temperature polysilicon active layer and between the low temperature polysilicon active layer and the inter layer dielectric layer;
wherein two vias are disposed on the inter layer dielectric layer, the low temperature polysilicon active layer comprises a source doped region and a drain doped region, the source layer and the drain layer are respectively connected to the source doped region and the drain doped region through the two vias of the inter layer dielectric layer, and controllable resistance spacer layers are disposed between the source layer and the source doped region or between the drain layer and the drain doped region while being not disposed between the source layer and the inter layer dielectric layer, and not disposed between the drain layer and the inter layer dielectric layer; wherein when a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current, and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current.

2. The array substrate according to claim 1 , wherein the controllable resistance spacer layers are an amorphous silicon layer, a concentration of an implanted ion of the source doped region and the drain doped region is greater than or equal to a first predetermined value, and the implanted ion is a boron ion, a phosphorus ion or an arsenic ion.

3. The array substrate according to claim 1 , wherein the controllable resistance spacer layers are an amorphous silicon layer, a concentration of an implanted ion of the source doped region and the drain doped region is less than a first predetermined value, and the implanted ion is a boron ion, a phosphorus ion or an arsenic ion;
an implanted ion with a concentration greater than or equal to a second predetermined value is doped to a side of the controllable resistance spacer layers positioned between the source layer and the source doped region near the source layer, an implanted ion with a concentration greater than or equal to a second predetermined value is doped to the drain layer and the drain doped region near the drain layer, and the implanted ion with the concentration greater than or equal to the second predetermined value is a boron ion, a phosphorus ion or an arsenic ion.

4. A liquid crystal display panel, comprising: an array substrate, a color filter substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate comprises a low temperature polysilicon active layer, a gate layer, an inter layer dielectric layer, a source layer and a drain layer formed on a substrate, the inter layer dielectric layer is disposed on the low temperature polysilicon active layer, the source layer and the drain layer is disposed on the inter layer dielectric layer, the gate layer is disposed on the low temperature polysilicon active layer and between the low temperature polysilicon active layer and the inter layer dielectric layer;
two vias are disposed on the inter layer dielectric layer, the low temperature polysilicon active layer comprises a source doped region and a drain doped region, the source layer and the drain layer are respectively connected to the source doped region and the drain doped region through the two vias of the inter layer dielectric layer, and controllable resistance spacer layers are disposed between the source layer and the source doped region or between the drain layer and the drain doped region while being not disposed between the source layer and the inter layer dielectric layer, and not disposed between the drain layer and the inter layer dielectric layer, wherein when a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current, and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current.

5. The liquid crystal display panel according to claim 4 , wherein the controllable resistance spacer layers are an amorphous silicon layer, a concentration of an implanted ion of the source doped region and the drain doped region is greater than or equal to a first predetermined value, and the implanted ion is a boron ion, a phosphorus ion or an arsenic ion.

6. The liquid crystal display panel according to claim 4 , wherein the controllable resistance spacer layers are an amorphous silicon layer, a concentration of an implanted ion of the source doped region and the drain doped region is less than a first predetermined value, and the implanted ion is a boron ion, a phosphorus ion or an arsenic ion;
an implanted ion with a concentration greater than or equal to a second predetermined value is doped to a side of the controllable resistance spacer layers positioned between the source layer and the source doped region near the source layer, an implanted ion with a concentration greater than or equal to a second predetermined value is doped to the drain layer and the drain doped region near the drain layer, and the implanted ion with the concentration greater than or equal to the second predetermined value is a boron ion, a phosphorus ion or an arsenic ion.

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd
• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng

Classifications

• H10P14/6903

  containing silicon · CPC title

• H10P14/63

  characterised by the formation processes · CPC title

• H10D64/0114

  to diamond, semiconducting diamond-like carbon or graphene · CPC title

• G02F1/1339 Primary

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F2201/501

  Blocking layers, e.g. against migration of ions · CPC title