Decision feedback equalizer with post-cursor non-linearity correction

Patent metadata

Field	Value
Publication number	US-10038575-B1
Application number	US-201715692202-A
Country	US
Kind code	B1
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

In some embodiments, a DFE including: an input terminal configured to receive an input signal carrying a plurality of symbols; an adder circuit coupled to the input terminal of the DFE; a plurality of comparator circuits configured to receive respective threshold signals; a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, where: the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and the plurality of correction coefficients are independently adjusted based on a previously received symbol.

First claim

What is claimed is:

1. A decision feedback equalizer (DFE) comprising:
an input terminal configured to receive an input signal carrying a plurality of symbols;
an adder circuit coupled to the input terminal of the DFE;
a plurality of comparator circuits configured to receive respective threshold signals;
a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and
a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, wherein:
the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and
the plurality of correction coefficients are independently adjusted based on a previously received symbol.

2. The DFE of claim 1 , further comprising a plurality of shift register taps coupled to respective outputs of respective slicer circuits.

3. The DFE of claim 1 , wherein the respective correction coefficients are adjusted by adjusting a single correction coefficient of the plurality of correction coefficients without adjusting other correction coefficients of the plurality of correction coefficients when a new symbol is received at the input terminal of the DFE.

4. The DFE of claim 1 , wherein the adder circuit is a first adder circuit of a plurality of adder circuits, wherein each adder circuit of the plurality of adder circuits is coupled to respective comparator circuits of the plurality of comparator circuits.

5. The DFE of claim 4 , wherein each adder circuit of the plurality of adder circuits, respective comparator circuits of the plurality of comparator circuits, respective multiplier circuits, and respective slicer circuits of the plurality of slicer circuits form respective adder and slicer circuits.

6. The DFE of claim 1 , wherein the input signal comprises a differential input signal.

7. The DFE of claim 1 , wherein the plurality of symbols comprises a plurality of pulse-amplitude modulation with four levels (PAM-4) symbols.

8. The DFE of claim 7 , wherein:
the plurality of comparator circuits comprises a high comparator circuit coupled to the adder circuit, a center comparator circuit coupled to the adder circuit, and a low comparator circuit coupled to the adder circuit;
the plurality of slicer circuits comprises a high slicer circuit coupled to the high comparator circuit, a center slicer circuit coupled to the center comparator circuit, and a low slicer circuit coupled to the low comparator circuit, the high slicer circuit configured to produce a high data bit, the center slicer circuit configured to produce a center data bit, and the low slicer circuit configured to produce a low data bit;
the plurality of correction coefficients comprises a high correction coefficient, a center correction coefficient, and a low correction coefficient; and
the plurality of multiplier circuits comprises a high multiplier circuit configured to multiply the high data bit times the high correction coefficient, a center multiplier circuit configured to multiply the center data bit times the center correction coefficient, and a low multiplier circuit configured to multiply the low data bit times the low correction coefficient.

9. The DFE of claim 8 , wherein an immediately preceding symbol of the plurality of symbols has a first level, and wherein adjusting respective correction coefficients comprises:
when the first level corresponds to a highest voltage, updating the high correction coefficient;
when the first level corresponds to a second highest voltage, updating the center correction coefficient; and
when the first level corresponds to a third highest voltage, updating the low correction coefficient.

10. The DFE of claim 9 , wherein the highest voltage corresponds to a first positive voltage, the second highest voltage corresponds to the first positive voltage divided by three plus a first constant, and the third highest voltage corresponds to a negative voltage.

11. The DFE of claim 10 , wherein the first constant is determined using statistical analysis based on an eye diagram of the PAM-4 symbols.

12. The DFE of claim 1 , wherein respective correction coefficients are determined using a least-mean-square (LMS) algorithm.

13. The DFE of claim 1 , further comprising a plurality of output terminals coupled to respective slicer circuits, wherein the plurality of slicer circuits is configured to produce thermometer encoded data bits based on the input signal at respective output terminals of the DFE.

14. The DFE of claim 1 , wherein the adder circuit comprises a resistively loaded adder circuit.

15. The DFE of claim 1 , wherein the adder circuit comprises a current integrating adder circuit.

16. The DFE of claim 1 , wherein the adder circuit comprises:
a differential output terminal;
a first plurality of differential pairs, each of the differential pairs of the first plurality of differential pairs coupled to the differential output terminal of the adder circuit;
a plurality of variable current sources coupled to respective differential pairs of the first plurality of differential pairs, wherein each tail current flowing through respective variable current sources of the plurality of variable current sources are independently controlled by respective correction coefficients; and
a second differential pair coupled to the differential output terminal of the adder circuit and coupled to the input terminal of the DFE.

17. The DFE of claim 16 , further comprising a plurality of current digital-to-analog converters (I-DACs) configured to generate respective tail currents flowing through respective variable current sources of the plurality of variable current sources.

18. A decision feedback equalizer (DFE) comprising:
an input terminal configured to receive an input signal carrying a plurality of symbols;
a plurality of adder circuits coupled to the input terminal of the DFE;
a plurality of comparator circuits coupled to respective adder circuits, the plurality of comparator circuits configured to receive respective threshold signals;
a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits;
a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results; and
a plurality of output terminals coupled to respective slicer circuits, wherein:
respective adder circuits are configured to subtract from the input signal respective plurality of multiplication results, and
respective correction coefficients are independently adjusted based on a previously received symbol.

19. The DFE of claim 18 , wherein adjusting respective correction coefficients comprises adjusting a single correction coefficient of the plurality of correction coefficients without adjusting other correction coefficients of the plurality of correction coefficients when a new symbol is received at the input terminal of the DFE.

20. The DFE of claim 18 , wherein the plurality of slicer c

Assignees

• St Microelectronics Srl

Inventors

• Steffan Giovanni
• Rossi Augusto Andrea
• Depaoli Emanuele

Classifications

• H04L25/03203

  Trellis search techniques · CPC title

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04L25/03267

  with decision feedback equalisers · CPC title