Pinfield crosstalk mitigation

Patent metadata

Field	Value
Publication number	US-10038281-B2
Application number	US-201514865220-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Aug 13, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A circuit board is provided including a top ground plane, a bottom ground plane, and a pin field of a connector with a plurality of pins that includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins. At least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs. One or more ground vias are provided on the circuit board positioned to correspond to the particular sideband pin.

First claim

What is claimed is:

1. An apparatus comprising:
a circuit board comprising
a top ground plane;
a bottom ground plane;
a pin field of a connector, wherein
the pin field comprises
a plurality of pins comprising
a plurality of differential pin pairs,
one or more ground pins, and
one or more sideband pins, wherein at least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs; and

one or more ground vias positioned closer to the particular sideband pin than the first pin of the first one of the differential pin pairs, at least a portion of the circuit board extending between the one or more ground vias and the particular sideband pin.

2. The apparatus of claim 1 , wherein the particular sideband pin is immediately between the first pin and a second pin of a second one of the differential pin pairs.

3. The apparatus of claim 2 , wherein the ground via provides a ground return for energy emitted by one or both of the first and second pins during signaling on one or both of the first and second differential pin pairs.

4. The apparatus of claim 3 , wherein the ground via mitigates crosstalk appearing on the particular sideband pin during signaling on either or both the first and second differential pin pairs.

5. The apparatus of claim 2 , wherein the plurality of pins further comprises a third pin and a fourth pin, and a particular one of the ground pins is positioned immediately between the third and fourth pins.

6. The apparatus of claim 5 , wherein the third pin is included in a third differential pin pair.

7. The apparatus of claim 5 , wherein the circuit board further comprises one or more additional ground vias corresponding to the particular ground pin.

8. The apparatus of claim 7 , wherein the third and fourth pins and ground pin are on an edge of the pin field and the one or more additional ground vias are positioned outside of the pin field.

9. The apparatus of claim 5 , wherein the third pin is included in the first differential pair and the fourth pin is included in the second differential pair.

10. The apparatus of claim 1 , wherein each ground via passes through the circuit board and is connected to both the top ground plane and to the bottom ground plane.

11. The apparatus of claim 1 , wherein the ground via is placed a minimum allowed distance from the particular sideband pin.

12. The apparatus of claim 1 , wherein the one or more ground vias comprise at least two ground vias.

13. The apparatus of claim 12 , wherein the at least two ground vias are aligned parallel to the first differential pair.

14. The apparatus of claim 12 , wherein the at least two ground vias are positioned to provide a path for routing of one or more conductive paths within the circuit board.

15. The apparatus of claim 1 , wherein the one or more ground vias comprise at least three ground vias positioned around the perimeter of the particular sideband pin.

16. The apparatus of claim 1 , wherein the pin field is laid out according to a PCIe-based specification.

17. The apparatus of claim 1 , wherein the sideband pin comprises a clock pin.

18. The apparatus of claim 1 , wherein the first differential pin pair corresponds to a high speed differential channel and the sideband pin corresponds to a lower speed sideband channel.

19. A system comprising:
a baseboard comprising a top ground plane and a bottom ground plane;
a connector; and
a card device connected to the baseboard by the connector,
wherein the connector comprises
a pin field comprising a plurality of pins, wherein the plurality of pins comprises a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins, wherein at least a particular one of the sideband pins is positioned within the pin field immediately between a first pin of a first one of the differential pin pairs and a second pin of a second one of the differential pin pairs; and
one or more ground vias positioned closer to the particular sideband pin than the first pin of the first one of the differential pin pairs, at least a portion of the baseboard extending between the one or more ground vias and the particular sideband pin, wherein the one or more ground vias connect to both the top and bottom ground planes of the baseboard.

20. An apparatus comprising:
a circuit board comprising a connector comprising
a pin field comprising a plurality of pins, wherein the plurality of pins comprises a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins, wherein at least a particular one of the sideband pins is positioned within the pin field immediately between a first pin of a first one of the differential pin pairs and a second pin of a second one of the differential pin pairs; and
a top ground plane;
a bottom ground plane; and
one or more ground vias positioned closer to the particular sideband pin than the first pin of the first one of the differential pin pairs, at least a portion of the circuit board extending between the one or more ground vias and the particular sideband pin, wherein the one or more ground vias connect to both the top and bottom ground planes.

21. The apparatus of claim 20 , wherein the one of more ground vias is placed a minimum allowed distance from the particular sideband pin.

22. The apparatus of claim 20 , wherein the ground vias mitigate against crosstalk appearing on the particular sideband pin during signaling on one or both of the first and second differential pin pairs.

Assignees

• Intel Corp

Inventors

• Wig Timothy D

Classifications

• H01R13/6471 Primary

  by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] · CPC title

• H01R12/718

  Contact members provided on the PCB without an insulating housing (contacts for abutting H01R12/714) · CPC title