Semiconductor transistor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10037914-B2
Application number	US-201715655920-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	Jun 13, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate having an active area and a trench isolation region surrounding the active area;
forming a gate oxide layer on the active area;
forming a gate on the gate oxide layer;
forming a spacer on a sidewall of the gate;
forming a doping region in the active area on either side of the gate;
depositing an insulating cap layer on the gate, the spacer, and the doping region;
forming an opening in the insulating cap layer, wherein the opening is situated above the gate or the doping region;
forming a redistributed contact layer (RCL) on the insulating cap layer, wherein the RCL fills into the opening and extends from the active area to the trench isolation region;
forming a contact etch stop layer (CESL) on the insulating cap layer and the RCL;
forming an inter-layer dielectric (ILD) layer on the CESL; and
forming a contact plug in the ILD layer and the CESL, wherein the contact plug is in direct contact with the RCL.

2. The method of fabricating a semiconductor device according to claim 1 , wherein the CESL comprises silicon nitride.

3. The method of fabricating a semiconductor device according to claim 1 , wherein after forming the spacer on the sidewall of the gate, the method further comprises:
trimming the spacer.

4. The method of fabricating a semiconductor device according to claim 1 , wherein the insulating cap layer is in direct contact with the spacer.

5. The method of fabricating a semiconductor device according to claim 1 , wherein the insulating cap layer comprises SiOx, SiN or SiON.

6. The method of fabricating a semiconductor device according to claim 1 , wherein the RCL comprises metal or metal silicide.

7. The method of fabricating a semiconductor device according to claim 1 , wherein the RCL comprises Ti, TiN, W, SiNix, SiCox, SiTix or SiWx.

8. The method of fabricating a semiconductor device according to claim 1 , wherein the doping region is a source doping region or a drain doping region.

9. The method of fabricating a semiconductor device according to claim 1 , wherein the contact plug comprises Ti, TiN or W.

Assignees

• United Microelectronics Corp

Inventors

• Zhou Zhibiao
• Chen Ding-Lung
• Zhang Xing Hua

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title