Device layer transfer with a preserved handle wafer section

Patent metadata

Field	Value
Publication number	US-10037911-B2
Application number	US-201715692666-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Dec 29, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

First claim

What is claimed is:

1. An assembly formed using a silicon-on-insulator substrate, the assembly comprising:
a device layer of the silicon-on-insulator substrate;
a buried dielectric layer of the silicon-on-insulator substrate, the buried dielectric layer having a first surface in contact with the device layer and a second surface;
a section of a handle wafer of the silicon-on-insulator substrate disposed on the second surface of the buried dielectric layer;
a device structure in the section of the handle wafer; and
a permanent substrate attached to the buried dielectric layer, the permanent substrate including a cavity configured to receive the section of the handle wafer.

2. The assembly of claim 1 wherein the cavity is dimensioned and positioned to receive the section of the handle wafer, the permanent substrate has a surface, and the second surface of the buried dielectric layer is coplanar with the surface of the permanent substrate.

3. The assembly of claim 2 wherein the section of the handle wafer has a thickness, and the cavity has a depth that is greater than the thickness of the section of the handle wafer to provide a clearance gap.

4. The assembly of claim 3 further comprising:
an adhesive layer configured to adhesively bond the permanent substrate to the buried dielectric layer,
wherein a portion of the adhesive layer is arranged in the clearance gap between the section of the handle wafer and the permanent substrate.

5. The assembly of claim 2 wherein the section of the handle wafer has a first size, and the cavity has a second size that is equal to the first size of the section of the handle wafer.

6. The assembly of claim 2 wherein the section of the handle wafer has a thickness and a width, the cavity has a depth that is 4 μm to 8 μm greater than the thickness of the section of the handle wafer, and the cavity has a width that is less than or equal to 30 μm greater than the width of the section of the handle wafer.

7. The assembly of claim 1 wherein the handle wafer 20 has a zero thickness adjacent to the section of the handle wafer.

8. The assembly of claim 1 further comprising:
an adhesive layer configured to adhesively bond the permanent substrate to the buried dielectric layer,
wherein the cavity is dimensioned and positioned to receive the section of the handle wafer with a portion of the adhesive layer between the section of the handle wafer and the permanent substrate.

9. The assembly of claim 1 wherein the device structure is formed at least partially in the device layer.

10. The assembly of claim 1 wherein the device structure includes one or more deep trench capacitors, the one or more deep trench capacitors extending through the device layer and the buried dielectric layer into the section of the handle wafer.

11. The assembly of claim 10 wherein a portion of the section of the handle wafer is disposed between the one or more deep trench capacitors and the permanent substrate.

12. The assembly of claim 1 wherein the permanent substrate has a surface, and the second surface of the buried dielectric layer is in direct contact with the surface of the permanent substrate.

13. The assembly of claim 1 wherein the permanent substrate is comprised of high resistance silicon, sapphire, quartz, or alumina.

Assignees

• Globalfoundries Inc

Inventors

• Stamper Anthony K
• Farooq Mukta G
• Fitzsimmons John A
• Jaffe Mark D
• Wolf Randy L

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title