Memory controller, memory system including the same and operating method thereof

Patent metadata

Field	Value
Publication number	US-10037816-B2
Application number	US-201715647987-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Dec 20, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. The detector may generate an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.

First claim

What is claimed is:

1. A memory controller comprising:
a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value; and
an inverter configured for inverting or non-inverting (inverting/non-inverting) the write data according to the check result of the detector,
wherein the detector generates an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.

2. The memory controller of claim 1 , wherein the detector enables a flag signal based on whether or not the number of bits having the first state among the plurality of bits constituting the write data is equal to or more than the reference value.

3. The memory controller of claim 2 , wherein the inverter inverts the write data based on the enabled flag signal.

4. The memory controller of claim 1 , further comprising an ECC (Error Correction Code) module configured for generating a parity bit to detect and correct (detect/correct) an error of the inverted and non-inverted (inverted/non-inverted) write data, and providing data of which an error is detected and corrected (detected/corrected) through the parity bit, as the read data.

5. A memory system comprising:
a memory device comprising a plurality of memory cells for storing data having a first or second state; and
a memory controller configured for writing or reading (writing/reading) a preset length of write or read (write/read) data to or from (to/from) the memory device,
wherein the memory controller inverts or non-inverts (inverts/non-inverts) the write data such that less than half of the inverted or non-inverted (inverted/non-inverted) data has the first state, and generates an error detection signal based on whether or not equal to or more than half of the read data has the first state.

6. The memory system of claim 5 , wherein the memory controller comprises:
a detector configured for enabling a flag signal based on whether or not equal to or more than half of the write data has the first state; and
an inverter configured for inverting and non-inverting the write data based on an enablement and disablement of the flag signal, respectively.

7. The memory system of claim 6 , wherein the detector generates the error detection signal based on whether or not equal to or more than half of the read data has the first state.

8. The memory system of claim 6 , wherein flag information indicating whether the write data is inverted or non-inverted is stored in the memory device with the inverted or non-inverted data.

9. The memory system of claim 8 , wherein the inverter inverts/non-inverts the read data based on the flag information, in response to the error detection signal, and outputs the inverted/non-inverted data to an outside.

10. The memory system of claim 6 , wherein the memory controller further comprises an ECC (Error Correction Code) module configured for generating a parity bit to detect and correct (detect/correct) an error of the inverted/non-inverted data, and providing data of which an error is detected and corrected (detected/corrected) through the parity bit, as the read data.

11. The memory system of claim 5 , wherein each memory cell includes a phase change material.

12. An operating method of a memory system, comprising:
checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value;
inverting or non-inverting the write data according to the check result;
storing the inverted or non-inverted data with flag information in a memory device, the flag information indicating whether the write data is inverted or non-inverted; and
generating an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data obtained by reading the stored data is equal to or more than the reference value.

13. The operating method of claim 12 , further comprising inverting or non-inverting (inverting/non-inverting) the read data based on the flag information, based on the error detection signal, and outputting the inverted or non-inverted (inverted/non-inverted) data to an outside.

14. The operating method of claim 12 , wherein the checking of whether the number of bits having the first state is less than the reference value comprises:
counting the number of bits having the first state;
comparing the count value to the reference value; and
enabling a flag signal based on whether or not the comparison result indicates that the count value is equal to or more than the reference value.

15. The operating method of claim 14 , wherein the inverting/non-inverting of the write data comprises inverting and non-inverting the write data based on an enablement and disablement of the flag signal, respectively.

16. The operating method of claim 12 , wherein the storing of the inverted or non-inverted data with the flag information comprises:
generating parity information to detect and correct (detect/correct) an error of the inverted or non-inverted data; and
storing the inverted or non-inverted data with the parity information in the memory device.

17. The operating method of claim 16 , wherein data of which an error is detected and corrected (detected/corrected) through the parity information are provided as the read data.

18. The operation method of claim 12 , wherein the memory device includes memory cells each comprising a phase change material.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sung-Eun
• Kwon Jung-Hyun
• JO Sang-Gu

Classifications

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H03M13/098

  using single parity bit · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title