Circuit for outputting information of a memory circuit during a self-refresh mode and related method thereof

Patent metadata

Field	Value
Publication number	US-10037787-B2
Application number	US-201715696200-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Sep 6, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

First claim

What is claimed is:

1. A circuit for outputting information of a memory circuit during a self-refresh mode, comprising:
a driver coupled to a self-refresh control circuit and a self-refresh address counter of the memory circuit for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode, wherein each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

2. The circuit of claim 1 , wherein the plurality of pads are used for outputting or receiving other predetermining signals after the memory circuit leaves the self-refresh mode.

3. The circuit of claim 1 , wherein the plurality of word lines correspond to one bank of the memory circuit, or correspond to a plurality of banks of the memory circuit.

4. The circuit of claim 1 , wherein after the memory circuit enters the self-refresh mode, the memory circuit executes data-refresh operation on memory cells coupled to the plurality of word lines in turn according to the plurality of inner signals.

5. The circuit of claim 1 , wherein the self-refresh control circuit generates the plurality of inner signals according to the self-refresh mode signal.

6. The circuit of claim 1 , wherein the self-refresh address counter counts to generate an address count according to an inner signal of the plurality of inner signals, and the driver outputs the address count, wherein the address count corresponds to an address of a word line of the plurality of word lines.

7. A method for outputting information of a memory circuit during a self-refresh mode, wherein a circuit applied to the method comprises a driver, the method comprising:
enabling a self-refresh mode signal and a test mode signal; and
the driver driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to the self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and the test mode signal are enabled and the memory circuit enters the self-refresh mode, wherein each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

8. The method of claim 7 , wherein, the plurality of pads are used for outputting or receiving other predetermining signals after the memory circuit leaves the self-refresh mode.

9. The method of claim 7 , wherein the plurality of word lines correspond to one bank of the memory circuit, or correspond to a plurality of banks of the memory circuit.

10. The method of claim 7 , wherein after the memory circuit enters the self-refresh mode, the memory circuit executes data-refresh operation on memory cells coupled to the plurality of word lines in turn according to the plurality of inner signals.

11. The method of claim 7 , wherein the plurality of inner signals are generated by a self-refresh control circuit of the memory circuit according to the self-refresh mode signal.

12. The method of claim 7 , wherein a self-refresh address counter of the memory circuit counts to generate an address count according to an inner signal of the plurality of inner signals, and the driver outputs the address count, wherein the address count corresponds to an address of a word line of the plurality of word lines.

13. A memory circuit capable of outputting information thereof during a self-refresh mode, the memory circuit comprising:
a self-refresh control circuit generating a plurality of inner signals corresponding to a self-refresh mode signal according to the self-refresh mode signal;
a self-refresh address counter generating an address count according to an inner signal of the plurality of inner signals;
an inner signal pad;
at least one address information pad; and
a driver coupled to the self-refresh control circuit, the self-refresh address counter, the inner signal pad, and the at least one address information pad, the driver comprising:
an inner signal driving circuit coupled to the inner signal pad; and
at least one address information driving circuit coupled to the at least one address information pad;
wherein the inner signal driving circuit outputs the inner signal to the inner signal pad, and the at least one address information driving circuit outputs the address count to the at least one address information pad.

14. The memory circuit of claim 13 , wherein the plurality of inner signals correspond to a plurality of word lines of the memory circuit.

15. The memory circuit of claim 14 , wherein the address count corresponds to an address of a word line of the plurality of word lines.

Assignees

• Etron Tech Inc

Inventors

• Shiah Chun
• Chen Ho-Yin
• Chang Cheng-Nan

Classifications

• G11C7/08 Primary

  Control thereof · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C29/50016

  of retention · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/46

  Test trigger logic · CPC title