Instruction and logic to provide vector blend and permute functionality

Patent metadata

Field	Value
Publication number	US-10037205-B2
Application number	US-201113977734-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

First claim

What is claimed is:

1. A processor comprising:
one or more vector registers each comprising a plurality of data fields to store values of vector elements;
a decode stage to decode a first instruction specifying: a destination operand of the one or more vector registers, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand; and
an execution unit, responsive to the decoded first instruction, to:
read index values from the plurality of data fields of the size of vector elements in the second operand, each of the plurality of index values having a first selector portion and a second selector portion;
merge vector element values of a first vector element and a second vector element of the data fields in accordance with the first selector portion to generate an intermediate vector;
store vector element values to a portion of corresponding data fields of the specified size of vector elements in the destination operand, wherein for each of the plurality of data fields, responsive to the respective first selector portion having a first value, a first vector element value is to be copied to a corresponding data field of an intermediate vector result of the intermediate vector from a corresponding data field of the specified size of vector elements in the first operand, and responsive to the respective first selector portion having a second value, a second vector element value is to be copied to the corresponding data field of the intermediate vector result from a corresponding data field of the specified size of vector elements in the third operand; and
replace, in the first operand, unmasked data fields of the size of the vector element with the merged vector element values of the data fields of the intermediate vector in accordance with the second vector element.

2. The processor of claim 1 , wherein the specified third operand is one of the one or more vector registers.

3. The processor of claim 1 , wherein the specified third operand is a memory location.

4. The processor of claim 1 , wherein each of the plurality of index values in the second operand has a first selector portion consisting of the most significant bit of the respective data field of the size of vector elements.

5. The processor of claim 4 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant four bits of the respective data field of the size of vector elements.

6. The processor of claim 4 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant three bits of the respective data field of the size of vector elements.

7. The processor of claim 4 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant two bits of the respective data field of the size of vector elements.

8. The processor of claim 1 , wherein the specified destination operand is also the specified first operand.

9. The processor of claim 1 , wherein the portion of corresponding data fields of the specified size of vector elements in the destination operand to be replaced are those data fields unmasked by a mask operand specified by the first instruction.

10. A machine implemented method comprising:
decoding, by a processor, a first instruction specifying: a destination operand of one or more vector registers each comprising a first plurality of data fields to store values of vector elements, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand; and
responsive to the decoded first instruction:
reading a plurality of index values from data fields of the size of vector elements in the second operand, each of the plurality of index values having a first selector portion and a second selector portion;
merging, by the processor, vector element values of a first vector element and a second vector element of the data fields in accordance with the first selector portion to generate an intermediate vector;
storing, by the processor, vector element values to a portion of corresponding data fields of the specified size of vector elements in the destination operand, wherein for each of the plurality of data fields, responsive to the respective first selector portion having a first value, a first vector element value is to be copied to a corresponding data field of an intermediate vector result of the intermediate vector from a corresponding data field of the specified size of vector elements in the first operand, and responsive to the respective first selector portion having a second value, a second vector element value is to be copied to the corresponding data field of the intermediate vector result from a corresponding data field of the specified size of vector elements in the third operand; and
replacing, by the processor in the first operand, unmasked data fields of the size of the vector element with the merged vector element values of the data fields of the intermediate vector in accordance with the second vector element.

11. The machine implemented method of claim 10 , wherein the specified third operand is one of the one or more vector registers.

12. The machine implemented method of claim 10 , wherein the specified third operand is a memory location.

13. The machine implemented method of claim 10 , wherein each of the plurality of index values in the second operand has a first selector portion consisting of the most significant bit of the respective data field of the size of vector elements.

14. The machine implemented method of claim 13 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant four bits of the respective data field of the size of vector elements.

15. The machine implemented method of claim 13 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant three bits of the respective data field of the size of vector elements.

16. The machine implemented method of claim 13 , wherein each of the plurality of index values in the second operand has a second selector portion consisting of the least significant two bits of the respective data field of the size of vector elements.

17. The machine implemented method of claim 10 , wherein the specified destination operand is also the specified first operand.

18. The machine implemented method of claim 10 , wherein the portion of corresponding data fields of the specified size of vector elements in the destination operand to be replaced are those data fields unmasked by a mask operand specified by the first instruction.

19. A processing system comprising:
a memory; and
a first plurality of processors, each of the first plurality of processors comprising:
one or more vector registers each comprising a first plurality of data fields to store values of vector elements;
a decode stage to decode a first instruction specifying: a destination operand of the one or more vector registers, a first operand of the one or more vector registers, a size of the vector elements, a second operand of the one or more vector registers, and a third operand; and
an execution unit, responsive to the decoded first instruction, to:
read a plurality of index values from data fields of the

Assignees

• Valentine Robert
• Toll Bret L
• Corbal Jesus
• Wiedemeier Jeffrey G
• Samudrala Sridhar
• Intel Corp

Inventors

• Valentine Robert
• Toll Bret L
• Corbal Jesus
• Wiedemeier Jeffrey G
• Samudrala Sridhar

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title