Data on clock lane of source synchronous links

Patent metadata

Field	Value
Publication number	US-10033518-B2
Application number	US-201715703792-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Jun 30, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

First claim

The invention claimed is:

1. A device, comprising:
a clock signal generator configured to generate a clock signal;
a data source;
a clock data driver coupled to the clock signal generator and to the data source, the clock data driver including a modulation circuit configured to generate a modulated clock signal, based on the clock signal, that encodes first data from the data source into the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data, the clock data driver modulates the amplitude of the clock signal between a first threshold value and a second threshold value, the first and second threshold values representing respective data values of the first data; and
a clock output coupled to the clock data driver, the clock output configured to output the modulated clock signal to a receiving device.

2. The device of claim 1 wherein the modulation circuit includes:
first and second output nodes;
a plurality of first switches, each of the first switches being coupled to a respective resistor between a first voltage node and the first output node;
a plurality of second switches, each of the second switches being coupled to a respective resistor between a second voltage node and the first output node;
a plurality of third switches, each of the third switches being coupled to a respective resistor between the first voltage node and the second output node; and
a plurality of fourth switches, each of the fourth switches being coupled to a respective resistor between the second voltage node and the second output node.

3. The device of claim 2 wherein the first voltage node has a voltage level that is two times a voltage level of the second threshold value.

4. The device of claim 3 wherein the voltage level of the first voltage node is four times a voltage level of the first threshold value.

5. The device of claim 2 wherein the second voltage node is coupled to an electrical ground.

6. The device of claim 2 wherein the clock data driver is configured to generate the modulated clock signal by selectively operating the first switches, the second switches, the third switches, and the fourth switches in synchronization with the clock signal.

7. The device of claim 1 wherein the modulation circuit includes:
first and second output nodes;
a plurality of supply voltage input nodes;
a plurality of first switches, each of the first switches coupled to a respective supply voltage input node;
a plurality of second switches, each of the second switches coupled to a respective supply voltage input node;
a first resistor coupled between the plurality of first switches and the first output node; and
a second resistor coupled between the plurality of second switches and the second output node.

8. The device of claim 7 wherein the clock data driver is configured to generate the modulated clock signal by selectively operating the first switches and the second switches in synchronization with the clock signal.

9. The device of claim 1 , further comprising a data output configured to output second data to the receiving device.

10. The device of claim 1 wherein both a rising edge and a falling edge of a clock cycle of the modulated clock signal indicate individual bits of the first data.

11. The device of claim 1 wherein the clock data driver modulates the amplitude of the modulated clock signal between at least four different threshold values, each threshold value representing a respective data value of the first data.

12. The device of claim 1 wherein the data source comprises at least one of a CPU and a camera sensor.

13. A method comprising:
generating a first clock signal in a data transmitting device;
generating, by a modulation circuit in the data transmitting device, a modulated clock signal that encodes first data in the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data, the amplitude of the clock signal being modulated between a first threshold value and a second threshold value, the first and second threshold values representing respective data values of the first data;
outputting the modulated clock signal from a clock output of the data transmitting device; and
outputting a data signal from a data output of the transmitting device, the data signal including second data.

14. The method of claim 13 wherein the modulation circuit includes:
a plurality of first switches, each of the first switches being coupled to a respective resistor between a first voltage node and a first output node;
a plurality of second switches, each of the second switches being coupled to a respective resistor between a second voltage node and the first output node;
a plurality of third switches, each of the third switches being coupled to a respective resistor between the first voltage node and a second output node; and
a plurality of fourth switches, each of the fourth switches being coupled to a respective resistor between the second voltage node and the second output node,
wherein generating the modulated clock signal includes selectively operating the first switches, the second switches, the third switches, and the fourth switches in synchronization with the first clock signal.

15. The method of claim 13 wherein the modulation circuit includes:
a plurality of first switches, each of the first switches coupled to a respective supply voltage input node;
a plurality of second switches, each of the second switches coupled to a respective supply voltage input node;
a first resistor coupled between the plurality of first switches and the first output node; and
a second resistor coupled between the plurality of second switches and the second output node,
wherein generating the modulated clock signal includes selectively operating the first switches and the second switches in synchronization with the first clock signal.

16. The method of claim 13 , further comprising:
receiving in a clock input of a data receiving device the modulated clock signal from the clock output;
retrieving in the receiving device the first data from the modulated clock signal;
receiving in a data input of the data receiving device the data signal; and
retrieving in the receiving device the second data from the data signal.

17. The method of claim 16 , further comprising:
providing the modulated clock signal to a comparator of the receiving device;
outputting a normalized clock signal from the comparator, the normalized clock signal having a constant amplitude and a same frequency as the modulated clock signal;
delaying the normalized clock signal by a variable delay circuit;
providing the delayed normalized clock signal to respective clock inputs of a plurality of flip-flops of the data receiving device;
providing the data signal, or a processed data signal derived from the data signal, to a first flip-flop of the plurality of flip-fops;
providing the modulated clock signal, or a processed clock data signal derived from the modulated clock signal, to a second flip-flop of the plurality of flip-fops; and
retrieving the first and second data from the first and second flip flops, respectively.

18. A system comprising:
a data transfer device including:
a clock signal generator configured to generate a clock signal;
a data source;
a clock data driver coupled to the clock signal generator and to the data source, the clock data driver including a modulation circuit configured to generate a modulated clock signal, bas

Assignees

• St Microelectronics Int Nv

Inventors

• Nandy Tapas
• Gupta Nitin

Classifications

• G06F13/4252

  using a handshaking protocol · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• G06F13/4208 Primary

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title