Dual mode power amplifier control interface with a multi-mode general purpose input/output interface

Patent metadata

Field	Value
Publication number	US-10033385-B2
Application number	US-201615388138-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Oct 24, 2011
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.

First claim

What is claimed is:

1. A digital control interface comprising:
a first interface device configured to provide a serial interface when active; and
a second interface device configured to provide a general purpose input/output interface when active, the first interface device inactive when the second interface device is active, the second interface device activated in response to a control signal corresponding to a first logic value, the second interface device including combinational logic configured to provide one or more input signals to the digital control interface to one or more level shifters when the control signal corresponds to the first logic value.

2. The digital control interface of claim 1 further comprising a control circuit that deactivates the first interface device in response to the control signal corresponding to the first logic value.

3. The digital control interface of claim 1 further comprising a control circuit that configures a register of the first interface device with a default signal value during activation of the first interface device.

4. The digital control interface of claim 1 wherein the activation of the first interface device is triggered by the control signal corresponding to a second logic value.

5. A digital control interface comprising:
a first interface device configured to provide a serial interface when active;
a second interface device configured to provide a general purpose input/output interface when active, the first interface device inactive when the second interface device is active, the second interface device activated in response to a control signal corresponding to a first logic value; and
a tri-state buffer, the tri-state buffer set to a first state when reading data from the first interface device and set to a second state when writing data to the first interface device.

6. The digital control interface of claim 5 wherein the digital control interface further includes a second tri-state buffer, the second tri-state buffer set to the first state when writing data from the first interface device and set to the second state when reading data from the first interface device.

7. A digital control interface comprising:
a front end core configured to provide a serial interface, the front end core in an active state when a configuration signal satisfies a first logic level and in an inactive state when the configuration signal does not satisfy the first logic level, the digital control interface configured to provide a general purpose input/output interface when the front end core is set to the inactive state; and
a combinational logic block configured to output a first enable signal and a first mode signal received from the front end core when the front end code is in an active state and to output a second enable signal and a second mode signal received from a pair of input pins when the front end code is in an inactive state.

8. The digital control interface of claim 7 wherein the digital control interface further includes a tri-state buffer, the tri-state buffer set to a first state when reading data from the front end core and set to a second state when writing data to the front end core.

9. The digital control interface of claim 8 wherein the digital control interface further includes a second tri-state buffer, the second tri-state buffer set to the first state when writing data from the front end core and set to the second state when reading data from the front end core.

10. The digital control interface of claim 8 further comprising a first set of level shifters configured to adjust a voltage level of one or more signals received from the front end core.

11. The digital control interface of claim 10 wherein the first set of level shifters are configured with a default state when the configuration signal does not satisfy the first logic level.

12. The digital control interface of claim 10 further comprising a second set of level shifters configured to adjust a voltage level of one or more signals received from the combinational logic block.

13. A power amplifier system comprising:
a power amplifier; and
an interface die that interfaces between the power amplifier and a signal source, the interface die configurable to provide a plurality of heterogeneous interfaces, the plurality of heterogeneous interfaces sharing at least a portion of hardware of the interface die, the interface die including a serial interface component that provides a serial interface when the interface die receives a mode selection signal of a first value, and the interface die including a general purpose input/output interface component that provides a general purpose input/output interface when the mode selection signal is of a second value.

14. The power amplifier system of claim 13 wherein the signal source provides the mode selection signal to the interface die.

15. The power amplifier system of claim 13 wherein the signal source is a transceiver.

16. The power amplifier system of claim 13 wherein the signal source is a mode selection device that determines a value of the mode selection signal based at least in part on an antenna signal.

17. The power amplifier system of claim 13 wherein the interface die further includes a control circuit that deactivates the serial interface component in response to a deactivation voltage signal and that configures a register of the serial interface component with a default signal value during activation of the serial interface component.

18. The power amplifier system of claim 13 wherein the general purpose input/output interface component includes combinational logic configured to provide general purpose input/output pin inputs to one or more level shifters when the mode selection signal is of the second value.

19. The power amplifier system of claim 13 wherein the interface die further includes a first tri-state buffer and a second tri-state buffer, the first tri-state buffer set to a first state when reading data from the serial interface component and set to a second state when writing data to the serial interface component, the second tri-state buffer set to the first state when writing data from the serial interface component and set to the second state when reading data from the serial interface component.

Assignees

• Skyworks Solutions Inc

Inventors

• Ripley David Steven

Classifications

• H03L5/02

  of power · CPC title

• H03F3/189

  High-frequency amplifiers, e.g. radio frequency amplifiers · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H04B2001/0408

  with power amplifiers · CPC title