Digital clock-duty-cycle correction

Patent metadata

Field	Value
Publication number	US-10033365-B2
Application number	US-201715598339-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	Oct 30, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

First claim

What is claimed is:

1. A clock generator, comprising:
a duty cycle correction circuit, comprising:
a charge pump comprising:
a current source;
a first output;
a second output;
a first switch; and
a second switch;
wherein the charge pump is configured to:
route current from the current source through the first switch to the first output during a positive portion of a clock; and
route current from the current source through the second switch to the second output during a negative portion of the clock; and

a controller configured to:
compare charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer;
generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

2. The clock generator of claim 1 , wherein the controller is configured to adjust the digital value to reduce the length of the one of the positive portion of the clock and the negative portion of the clock that is longer.

3. The clock generator of claim 1 , further comprising one or more capacitors coupled to the current source to accumulate charge provided by the first output and the second output.

4. The clock generator of claim 1 , further comprising:
a digital-to-analog converter coupled to the controller; and
a pulse width adjuster coupled to the digital-to-analog converter;
wherein the digital-to-analog converter is configured to convert the digital value to an analog signal, and the pulse width adjuster is configured to set the duty cycle of the clock based on the analog signal.

5. The clock generator of claim 1 , wherein the controller is configured to reset the charge accumulated from the first output and the charge accumulated from the second output by setting the first output and the second output to a same voltage prior to an initial one of the plurality of clock cycles.

6. The clock generator of claim 1 , further comprising calibration circuitry comprising:
a clock circuit configured to produce a calibration clock having a 50% duty cycle;
a multiplexer to route the calibration clock to the charge pump;
a digital-to-analog converter coupled to one of the charge pump and a comparator that compares the charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles; and
a calibration controller that identifies offset in the clock generator as a value applied to the digital-to-analog converter to change a value of output of the comparator while the calibration clock is applied to the charge pump.

7. A clock duty cycle correction circuit comprising:
a charge pump comprising:
a current source;
a first current output terminal;
a second current output terminal;
a first clock input terminal;
a second clock input terminal; and
a first transistor coupled to the current source, the first clock input terminal, and the first current output terminal to connect the current source to the first output terminal based on assertion of a clock signal at the first clock input terminal;
a second transistor coupled to the current source, the second clock input terminal, and the second current output terminal to connect the current source to the second output terminal based on assertion of an inverted version of the clock signal at the second clock input terminal;
a reset terminal; and
a reset transistor coupled to the first current output terminal, the second current output terminal, and the reset terminal to short the first current output terminal to the second current output terminal based on assertion of a reset signal at the reset terminal; and

a controller configured to:
compare charge accumulated from the first current output to charge accumulated from the second current output over a plurality of cycles of the clock signal to determine which of a positive portion of the clock signal and a negative portion of the clock signal is longer; and
generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on which of the positive portion of the clock signal and the negative portion of the clock signal is longer.

8. The clock duty cycle correction circuit of claim 7 , further comprising one or more capacitors coupled to the charge pump to accumulate charge provided by the first current output and the second current output.

9. The clock duty cycle correction circuit of claim 7 , further comprising:
a digital-to-analog converter coupled to the controller; and
a pulse width adjuster coupled to the digital-to-analog converter;
wherein the digital-to-analog converter is configured to convert the digital value to an analog signal, and the pulse width adjuster is configured to set the duty cycle of the clock based on the analog signal.

10. The clock duty cycle correction circuit of claim 7 , wherein the controller is configured to zero the charge accumulated from the first current output and the charge accumulated from the second current output by asserting the reset signal at the reset terminal prior to an initial one of the plurality of clock cycles.

11. The clock duty cycle correction circuit of claim 7 , further comprising:
calibration circuitry comprising:
a clock circuit configured to produce a calibration clock having a 50% duty cycle;
a multiplexer to route the calibration clock to the charge pump;
a digital-to-analog converter coupled to one of the charge pump and a comparator that compares the charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles;
a calibration controller that identifies offset in the clock generator as a value applied to the digital-to-analog converter to change a value of output of the comparator while the calibration clock is applied to the charge pump.

Assignees

• Texas Instruments Inc

Inventors

• Elbadry Mohammad
• Payne Robert Floyd
• Schuppener Gerd

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K2005/00026

  controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter · CPC title