Rectifier and regulator circuit

Patent metadata

Field	Value
Publication number	US-10033296-B1
Application number	US-201615255010-A
Country	US
Kind code	B1
Filing date	Sep 1, 2016
Priority date	Sep 1, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Systems and methods for rectifying and regulating an input voltage are disclosed. A biasing circuit is configured to generate a biasing voltage greater than the maximum value of the input voltage minus a forward bias voltage of a p-n junction diode and apply the biasing voltage to the body terminal of a MOSFET. The biasing circuit may generate the biasing voltage by rectifying the input voltage. A control circuit is configured to generate a gate voltage based on the rectified and regulated output voltage and apply the gate voltage to the gate terminal of the MOSFET.

First claim

What is claimed is:

1. A method of rectifying and regulating an input voltage using a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET having a first terminal, a second terminal, a gate terminal, and a body terminal, the method comprising:
receiving an input voltage;
generating a biasing voltage, the biasing voltage being higher than a maximum value of the input voltage minus a forward bias voltage of a p-n junction diode;
applying the biasing voltage to the body terminal of the MOSFET;
applying the input voltage to the first terminal of the MOSFET; and
regulating transfer of current from the first terminal of the MOSFET to the second terminal of the MOSFET to generate a voltage at the second terminal of the MOSFET.

2. The method of claim 1 , wherein regulating transfer of current from the first terminal to the second terminal comprises allowing current to flow between the first terminal and the second terminal when the input voltage is greater than the voltage at the second terminal and the input voltage is greater than the voltage at the gate terminal plus a threshold voltage of the MOSFET.

3. The method of claim 1 , wherein regulating transfer of current from the first terminal to the second terminal comprises controlling the voltage at the gate terminal such that the voltage at the second terminal corresponds with a reference voltage.

4. The method of claim 3 , wherein the controlling of the voltage at the gate terminal comprises providing the voltage at the second terminal of the MOSFET to a non-inverting input of an error amplifier, providing the reference voltage to an inverting input of the error amplifier, and providing an output of the error amplifier to the gate terminal of the MOSFET.

5. The method of claim 3 , wherein the controlling of the voltage at the gate terminal comprises preventing the voltage at the gate terminal from decreasing if the voltage at the second terminal is lower than the voltage at the gate terminal minus a threshold voltage of the MOSFET.

6. The method of claim 1 , wherein the biasing voltage is generated from the input voltage.

7. The method of claim 1 , wherein generating the biasing voltage comprises rectifying the input voltage.

8. The method of claim 7 , wherein the rectifying is performed utilizing a rectifier with a voltage drop lower than the forward bias voltage of a p-n junction diode.

9. The method of claim 7 , wherein the rectifying is performed utilizing a Schottky diode.

10. The method of claim 7 , wherein the rectifying is performed utilizing a diode-connected NMOS transistor.

11. The method of claim 1 , wherein the generating of the biasing voltage comprises utilizing the input voltage as the biasing voltage when the input voltage is greater than the voltage at the second terminal, and utilizing the voltage at the second terminal as the biasing voltage when the voltage at the second terminal is greater than the input voltage.

12. The method of claim 1 , wherein regulating transfer of current from the first terminal to the second terminal is rectifying the input voltage and regulating the voltage at the second terminal.

13. A system for rectifying and regulating an input voltage comprising:
a metal-oxide-semiconductor field-effect transistor (MOSFET) having a first terminal, a second terminal, a gate terminal, and a body terminal;
a biasing circuit coupled to the first terminal and to the body terminal, the biasing circuit being configured to generate a biasing voltage greater than the maximum value of a voltage on the first terminal minus a forward bias voltage of a p-n junction diode and apply the biasing voltage to the body terminal; and
a control circuit coupled to the gate terminal and the second terminal, the control circuit being configured to generate a gate voltage based on a voltage at the second terminal, and apply the gate voltage to the gate terminal to regulate transfer of current by the MOSFET from the first terminal to the second terminal.

14. The system of claim 13 , wherein the control circuit generates the gate voltage such that current flows between the first terminal and the second terminal when the voltage at the first terminal is greater than the voltage at the second terminal and the voltage at the first terminal is greater than the voltage at the gate terminal plus a threshold voltage of the MOSFET.

15. The system of claim 13 , wherein generating the gate voltage based on the voltage at the second terminal is generating the gate voltage such that the voltage at the second terminal has a regulated DC value.

16. The system of claim 13 , wherein the control circuit comprises an error amplifier, a non-inverting input of the error amplifier is coupled to the second terminal of the MOSFET, an inverting input of the error amplifier is coupled to a reference voltage, and an output of the error amplifier is coupled to the gate terminal of the MOSFET.

17. The system of claim 16 , wherein the control circuit comprises an overdrive protection transistor, a gate terminal of the overdrive protection transistor being coupled to the gate terminal of the MOSFET, a first terminal of the overdrive protection transistor being coupled to the second terminal of the MOSFET, and a second terminal of the overdrive protection transistor being coupled to the error amplifier such that if the overdrive protection transistor conducts an overdrive protection current to the error amplifier, the error amplifier will prevent the gate voltage from decreasing.

18. The system of claim 13 , wherein the biasing circuit is an auxiliary rectifier configured to rectify the voltage at the first terminal.

19. The system of claim 18 , wherein the auxiliary rectifier comprises a Schottky diode.

20. The system of claim 18 , wherein the auxiliary rectifier comprises a diode-connected NMOS transistor.

21. The system of claim 13 , wherein the biasing circuit is further coupled to the second terminal of the MOSFET, and wherein the biasing circuit is further configured to apply the higher of the voltage at the first terminal and the voltage at the second terminal to the body terminal.

22. The system of claim 13 , wherein the control circuit generates the gate voltage to regulate transfer of current by the MOSFET such that the MOSFET rectifies the voltage at the first terminal and regulates the voltage at the second terminal.

Assignees

• The Alfred E Mann Foundation For Scient Research

Inventors

• Lee Edward K F

Classifications

• H02M7/217 Primary

  using semiconductor devices only · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M7/2195

  the switches being synchronously commutated at the same frequency of the AC input voltage · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title