Thin-film transistor with crystallized active layer, method of manufacturing the same, and organic light-emitting display device including the same

Patent metadata

Field	Value
Publication number	US-10032922-B2
Application number	US-201514834581-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Nov 21, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A thin-film transistor, including a substrate; an active layer on the substrate; a gate electrode on the active layer; and a gate insulating layer between the active layer and the gate electrode, the active layer including a channel region; source and drain regions at opposite sides of the channel region; and lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element.

First claim

What is claimed is:

1. A thin-film transistor, comprising:
a substrate;
an active layer on the substrate, wherein the active layer has a uniform thickness;
a gate electrode on the active layer; and
a gate insulating layer between the active layer and the gate electrode, wherein the active layer is crystallized and includes:
a channel region;
source and drain regions at opposite sides of the channel region; and
lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element,
wherein cross-sectional areas of the lightly doped regions in a direction parallel to a surface of the substrate continuously decrease in a direction away from the substrate, the cross-sectional areas having pointed upper surfaces and vertical sidewalls.

2. The thin-film transistor as claimed in claim 1 , wherein a diffusion coefficient of the second element with respect to silicon is greater than a diffusion coefficient of the first element with respect to silicon.

3. The thin-film transistor as claimed in claim 2 , wherein the source and drain regions include silicide.

4. The thin-film transistor as claimed in claim 3 , wherein the first element includes one or more of boron (B), titanium (Ti), nickel (Ni), or zinc (Zn).

5. The thin-film transistor as claimed in claim 2 , wherein the second element includes one or more of titanium (Ti), nickel (Ni), or zinc (Zn), iron (Fe), copper (Cu), gold (Au), or silver (Ag).

6. The thin-film transistor as claimed in claim 5 , wherein side surfaces of the lightly doped regions contacting the channel region are not perpendicular to the surface of the substrate.

7. The thin-film transistor as claimed in claim 1 , wherein each one of the lightly doped regions includes a first side surface contacting the source and drain regions and a second side surface contacting the channel region, the first side surfaces being the vertical sidewalls that are perpendicular to the surface of the substrate, and the second side surfaces intersecting with the first side surfaces to define sharp points at the pointed upper surfaces.

8. The thin-film transistor as claimed in claim 7 , wherein the gate electrode overlaps the lightly doped regions.

9. A method of manufacturing a thin-film transistor, the method comprising:
forming one pair of precursor layers and an amorphous silicon layer on a substrate;
forming an active layer by crystallizing the amorphous silicon layer, wherein the active layer has a uniform thickness;
forming a gate insulating layer on the active layer; and
forming a gate electrode on the gate insulating layer,
wherein the one pair of precursor layers includes first and second elements that are different from each other, and
wherein forming the active layer includes:
forming a channel region by crystallizing the amorphous silicon layer;
forming source and drain regions by diffusing the first element into the amorphous silicon layer during crystallization of the amorphous silicon layer; and
forming lightly doped regions by diffusing the second element into the amorphous silicon layer during crystallization of the amorphous silicon layer, such that cross-sectional areas of the lightly doped regions in a direction parallel to a surface of the substrate continuously decrease in a direction away from the substrate, the cross-sectional areas having pointed upper surfaces and vertical sidewalls.

10. The method as claimed in claim 9 , wherein:
the second element is diffused to a wider area than the first element in the amorphous silicon layer,
the source and drain regions are formed at opposite sides of the channel region, and
the lightly doped regions are formed between the channel region and the source region and between the channel region and the drain region.

11. The method as claimed in claim 10 , wherein:
forming the one pair of precursor layers is performed after forming the amorphous silicon layer, and
the one pair of precursor layers are formed on the amorphous silicon layer at locations corresponding to where the source and drain regions are to be formed.

12. The method as claimed in claim 10 , wherein the source and drain regions include silicide.

13. The method as claimed in claim 10 , wherein:
forming the amorphous silicon layer is performed after forming the one pair of precursor layers, and
the amorphous silicon layer covers the one pair of precursor layers.

14. The method as claimed in claim 13 , wherein:
side surfaces of the lightly doped regions contacting the channel region are not perpendicular to the surface of the substrate, and
side surfaces of the lightly doped regions contacting the source and drain regions are the vertical sidewalls that are perpendicular to the surface of the substrate.

15. The method as claimed in claim 14 , wherein the gate electrode overlaps the lightly doped regions.

16. The method as claimed in claim 9 , wherein forming the one pair of precursor layers is performed by a sputtering method using a target including the first and second elements.

17. The method as claimed in claim 16 , wherein an amount of the first element in the target is greater than an amount of the second element in the target.

18. An organic light-emitting display device, comprising:
a substrate;
a thin-film transistor on the substrate; and
an organic light-emitting diode electrically connected to the thin-film transistor, the thin-film transistor including:
an active layer on the substrate, wherein the active layer has a uniform thickness;
a gate electrode on the active layer; and
a gate insulating layer between the active layer and the gate electrode, wherein the active layer is crystallized and includes:
a channel region;
source and drain regions at opposite sides of the channel region; and
lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element,
wherein cross-sectional areas of the lightly doped regions in a direction parallel to a surface of the substrate continuously decrease in a direction away from the substrate, the cross-sectional areas having pointed upper surfaces and vertical sidewalls.

19. The organic light-emitting display device as claimed in claim 18 , wherein the source and drain regions include silicide.

20. The organic light-emitting display device as claimed in claim 18 , wherein the gate electrode overlaps the lightly doped regions.

Assignees

• Samsung Display Co Ltd

Inventors

• Kishimoto Katsushi

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H01L29/78675 Primary

  Electricity · mapped topic

• H01L29/78621

  Electricity · mapped topic

• H01L29/66757

  Electricity · mapped topic

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title