Semiconductor device

Patent metadata

Field	Value
Publication number	US-10032736-B2
Application number	US-201414494409-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Sep 24, 2013
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip of a substantially rectangular shape having a main surface, a rear surface opposite the main surface, a first side, a second side opposite the first side, a substrate, an epitaxial layer formed on the substrate, a source electrode formed on the epitaxial layer, a drain electrode formed on the epitaxial layer and a gate electrode formed on the epitaxial layer,
the source electrode having a first portion extending in a first direction from the first side to the second side and a second portion extending from the first portion of the source electrode forward a first portion of the drain electrode,
the drain electrode having the first portion extending in the first direction and a second portion extending from the first portion of the drain electrode forward the first portion of the source electrode,
the gate electrode arranged between the first portion of the source electrode and the first portion of the drain electrode;

a plurality of lead frames including a source lead which is arranged outside of the semiconductor chip, a drain lead which is arranged outside of the semiconductor chip, a gate lead which is arranged outside of the semiconductor chip and a die pad on which the semiconductor chip is mounted;
a plurality of bonding wires including a first bonding wire via which the source electrode is electrically connected with the source lead, a second bonding wire via which the drain electrode is electrically connected with the drain lead and a third bonding wire via which the gate electrode is electrically connected with the gate lead; and
a resin package sealing the semiconductor chip, a portion of each of the plurality of lead frames and the plurality of bonding wires,
wherein in a plan view, the first portion of the source electrode and the first portion of the drain electrode extend in parallel to each other in the first direction,
wherein in the plan view, the second portion of the source electrode and the second portion of the drain electrode extend in parallel to each other in a second direction that is perpendicular to the first direction,
wherein the first bonding wire is electrically connected with the source electrode at a plurality of bonding points which are arranged in the first direction,
wherein, in cross sectional view, the first bonding wire is spaced apart from the source electrode between adjacent bonding points,
wherein the second bonding wire is electrically connected with the drain electrode at a plurality of bonding points which are arranged in the first direction, and
wherein, in cross sectional view, the second bonding wire is spaced apart from the drain electrode between adjacent bonding points.

2. The semiconductor device according to claim 1 , wherein the source lead is located outside of the first side of the semiconductor chip, and wherein the drain lead is located outside of the second side of the semiconductor chip.

3. The semiconductor device according to claim 2 ,
wherein the gate lead is located outside of the first side of the semiconductor chip,
wherein a gate pad is formed on the epitaxial layer of the semiconductor chip and is located closer to the first side of the semiconductor chip than the second side of the semiconductor chip in the plan view,
wherein the gate pad is electrically connected with the gate electrode, and
wherein the gate pad is electrically connected with the gate lead by the third bonding wiring.

4. The semiconductor device according to claim 1 ,
wherein an end portion of the second portion of the source electrode is terminated at the vicinity of the first portion of the drain electrode than the first portion of the source electrode, and
wherein an end portion of the second portion of the drain electrode is terminated at the vicinity of the first portion of the source electrode than the first portion of the drain electrode.

5. The semiconductor device according to claim 1 ,
wherein the source lead has a first portion extending in the second direction and a plurality of second portions extending from the first portion of the source lead forward outside of the resin package, and
wherein an end portion of each of the second portions of the source lead is exposed from the resin package.

6. The semiconductor device according to claim 5 ,
wherein the drain lead has a first portion extending in the second direction and a plurality of second portions extending from the first portion of the drain lead forward outside of the resin package,
wherein an end portion of each of the second portions of the drain lead is exposed from the resin package.

7. The semiconductor device according to claim 6 ,
wherein the gate lead has a first portion extending in the second direction and a plurality of second portions extending from the first portion of the gate lead forward outside of the resin package, and
wherein an end portion of each of the second portions of the gate lead is exposed from the resin package.

8. The semiconductor device according to claim 1 ,
wherein a portion of the gate electrode is arranged between the second portion of the source electrode and the second portion of the drain electrode in the plan view.

9. The semiconductor device according to claim 1 , wherein the epitaxial layer includes a buffer layer, a channel layer and a barrier layer.

10. A semiconductor device comprising:
a semiconductor chip of a substantially rectangular shape having a main surface, a rear surface opposite the main surface, a first side, a second side opposite the first side, a substrate, an epitaxial layer formed on the substrate, a first electrode formed on the epitaxial layer, a second electrode formed on the epitaxial layer and a third electrode formed on the epitaxial layer,
the first electrode having a first portion extending in a first direction from the first side to the second side and a second portion extending from the first portion of the first electrode forward a first portion of the second electrode,
the second electrode having the first portion extending in the first direction and a second portion extending from the first portion of the second electrode forward the first portion of the first electrode,
the third electrode arranged between the first potion of the first electrode and the first portion of the second electrode;

a plurality of lead frames including a first lead which is arranged outside of the semiconductor chip, a second lead which is arranged outside of the semiconductor chip, a third lead which is arranged outside of the semiconductor chip and a die pad on which the semiconductor chip is mounted;
a plurality of bonding wires including a first bonding wire via which the first electrode is electrically connected with the first lead, a second bonding wire via which the second electrode is electrically connected with the second lead and a third bonding wire via which the third electrode is electrically connected with the third lead; and
a resin package sealing the semiconductor chip, a portion of each of the plurality of lead frames and the plurality of bonding wires,
wherein in a plan view, the first portion of the first electrode and the first portion of the second electrode extend in parallel to each other in the first direction,
wherein in the plan view, the second portion of the first electrode and the second portion of the second electrode extend in parallel to each other in a second direction that is perpendicular to the first direction,
wherein the first bonding wire is electrically connected with the first lead and the first electrode at a plurality of first bonding points,
wherein the plurality of first bonding points includ

Assignees

• Renesas Electronics Corp

Inventors

• Miura Yoshinao
• Nakamura Takashi
• Danno Tadatoshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title