Embedding thin chips in polymer

US10032709B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10032709-B2
Application numberUS-201715412993-A
CountryUS
Kind codeB2
Filing dateJan 23, 2017
Priority dateOct 9, 2012
Publication dateJul 24, 2018
Grant dateJul 24, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

First claim

Opening claim text (preview).

What is claimed: 1. An apparatus comprising: A) a substrate comprising a standoff well region, wherein: the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and B) a sensor disposed within the standoff well region on a portion of the exposed flexible and stretchable polymer proximate to the standoff. 2. The apparatus of claim 1 , wherein the sensor is embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff. 3. The apparatus of claim 1 , wherein a height of the standoff greater than or about equal to a height of the sensor. 4. The apparatus of claim 1 , wherein the standoff completely surrounds the sensor. 5. The apparatus of claim 1 , wherein the standoff includes at least one gap between a plurality of standoffs that define the standoff well region. 6. An apparatus comprising: A) a substrate comprising a standoff well region, wherein: the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and B) an electrical interconnect disposed within the standoff well region on a portion of the exposed flexible and stretchable polymer proximate to the standoff. 7. The apparatus of claim 6 , wherein the electrical interconnect is embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff. 8. The apparatus of claim 6 , wherein a height of the standoff greater than or about equal to a height of the electrical interconnect. 9. The apparatus of claim 6 , wherein the electrical interconnect is a stretchable serpentine interconnect. 10. The apparatus of claim 6 , wherein the electrical interconnect is one or more interconnects electrically connecting a plurality of device islands. 11. The apparatus of claim 10 , wherein a height of the standoff is greater than or equal to a height of the one or more electrical interconnects and the plurality of device islands. 12. The apparatus of claim 10 , wherein the plurality of device islands include one or more thinned chips disposed on the flexible and stretchable polymer. 13. The apparatus of claim 10 , further comprising at least one additional layer disposed on the first conductive material or on the flexible and stretchable polymer, wherein the at least one additional layer positions the one or more interconnects and the plurality of device islands at a neutral mechanical plane of the apparatus. 14. The apparatus of claim 6 , wherein the standoff completely surrounds the electrical interconnect. 15. The apparatus of claim 6 , wherein the standoff includes at least one gap between a plurality of standoffs that define the standoff well region. 16. A method for embedding electrical interconnects, the method comprising: A) providing a substrate comprising a standoff well region, wherein: the substrate comprises a layer of a first conductive material disposed on a layer of a flexible and stretchable polymer, and a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible and stretchable polymer, thereby forming the standoff well region; and B) disposing an electrical interconnect on a portion of the exposed flexible and stretchable polymer proximate to the standoff. 17. The method of claim 16 , wherein the electrical interconnect is further embedded in the portion of the exposed flexible and stretchable polymer proximate to the standoff. 18. The method of claim 16 , wherein the electrical interconnect is a stretchable serpentine interconnect. 19. The method of claim 16 , wherein the electrical interconnect is a one or more interconnects electrically connecting a plurality of device islands.

Assignees

Inventors

Classifications

  • comprising holes having chips therein · CPC title

  • Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

  • On different surfaces · CPC title

  • Bond pads specially adapted therefor · CPC title

  • Bond pads being integral with underlying chip-level interconnections · CPC title

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Frequently asked questions

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What does patent US10032709B2 cover?
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, wher…
Who is the assignee on this patent?
Mc10 Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/688. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).