Detecting circuit design flaws based on timing analysis

Patent metadata

Field	Value
Publication number	US-10031995-B2
Application number	US-201514858040-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

First claim

What is claimed is:

1. A method comprising:
performing a static timing analysis simulation run on an electronic circuit design to determine projected timing of the electronic circuit, absent a full simulation of the electronic circuit, the static timing analysis run producing end point results for the electronic circuit design;
automatically processing, by an electronic circuit design tool, the end point results for the electronic circuit design, including:
loading the end point results of the static timing analysis run, the results being obtained from the static timing analysis simulation to determine the projected timing of the electronic circuit absent the full simulation of the electronic circuit;
selecting a path from said loaded results;
providing technology specific context data denoting characteristic device values for specific device type manufactures using specific manufacturing technologies;
determining for one or more test points of the selected path, design quality parameters for determining a design problem area, the one or more test points corresponding to one or more device pins in the electronic circuit design;
determining, for the design problem area, a root cause by analyzing design problem area data in comparison to related ones of said technology specific context data, the root cause being identified as having a highest relative problem importance;

automatically generating, by the electronic circuit design tool, at least one design change for enhancing the electronic circuit based on the automatic processing to facilitate meeting predefined design criteria for the electronic circuit, the at least one design change addressing the root cause of the design problem area; and
providing, by the electronic circuit design tool, the automatically generated at least one design change for use in fixing the design problem area of the root cause of the electronic circuit design;
manufacturing the electronic circuit pursuant to the electronic circuit design as fixed via the at least one design change.

2. The method according to claim 1 , wherein said technology specific context data comprises at least one of a threshold value, a typical delay, or a maximum slew value for one or more timing phases.

3. The method according to claim 1 , wherein said design quality parameters comprise at least one of a high delay, a signal slew, or a placement of a device within a layout of said electronic circuit.

4. The method according to claim 3 , wherein based on said design quality parameters comprising the placement, the computer-implemented method further comprises:
determining one test point position, the one test point position being a last or a penultimate test point position;
determining a placement delta of a current test point in relation to said one test point position;
loading a global path direction vector;
determining whether said placement delta is following said global path direction vector;
determining whether said placement delta is above an ignore placement mismatch threshold; and
determining whether said placement delta is above a critical placement mismatch threshold.

5. The method according to claim 1 , wherein at least one of a color rendering attribute or a test point design quality parameter is assigned to a test point relating to the design problem area.

6. The method according to claim 1 , wherein a test point of the one or more test points is selected out of a group comprising a pin, a wire delay, an adjust, a device delay, and an assertion.

7. The method according to claim 6 , wherein based on said test point being of a type wire delay, the computer-implemented method further comprises:
determining a source pin load and a related sink pin slew.

8. The method according to claim 6 , wherein based said test point being of a type device delay, the computer-implemented method further comprises:
analyzing at least one of a device, a buffer, or a latch.

9. The method according to claim 8 , wherein said analyzing said device comprises:
determining at least one of a device voltage threshold value, a device primary output slew value, or a device primary output load value in comparison to a device size, and a device fan out value.

10. The method according to claim 8 , wherein based on said device being analyzed being a buffer, the computer-implemented method further comprises:
determining a warning threshold value and an error threshold for a primary input slew of the buffer;
based on a primary input slew value of said buffer being better than a primary output slew value of said buffer, reporting an obsolete buffer error message; and
based on said primary input slew value being better than an error threshold value, reporting an obsolete buffer error message.

11. The method according to claim 8 , wherein said device being analyzed is a latch, and wherein said analyzing comprises:
identifying a latch type; and
loading a local clock wire delay value, a slew value, and a fan-out value from a previous test point in said selected path.

12. A computer system comprising:
a memory; and
a processing device in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
performing a static timing analysis simulation run on an electronic circuit design to determine projected timing of the electronic circuit, absent a full simulation of the electronic circuit, the static timing analysis run producing end point results for the electronic circuit design;
automatically processing, by an electronic circuit design tool, the end point results for the electronic circuit design, including:
loading the end point results of the static timing analysis run, the results being obtained from the static timing analysis simulation to determine the projected timing of the electronic circuit absent the full simulation of the electronic circuit;
selecting a path from said loaded results;
providing technology specific context data denoting characteristic device values for specific device type manufactures using specific manufacturing technologies;
determining for one or more test points of the selected path, design quality parameters for determining a design problem area, the one or more test points corresponding to one or more device pins in the electronic circuit design;
determining, for the design problem area, a root cause by analyzing design problem area data in comparison to related ones of said technology specific context data, the root cause being identified as having a highest relative problem importance;

automatically generating, by the electronic circuit design tool, at least one design change for enhancing the electronic circuit based on the automatic processing to facilitate meeting predefined design criteria for the electronic circuit, the at least one design change addressing the root cause of the design problem area; and
providing, by the electronic circuit design tool, the automatically generated at least one design change for use in fixing the design problem area of the root cause of the electronic circuit; and
manufacturing the electronic circuit pursuant to the electronic circuit design as fixed via the at least one design change.

13. The computer system according to claim 12 , wherein said design quality parameters comprise at least one of a high delay, a signal slew, or a placement of a device within a layout of said electronic circuit.

14. The computer system according to claim 13 , wherein based on said design quality parameters comprising the placement, the method further comprises:
determining one test point position, the one tes

Assignees

• IBM

Inventors

• Haller Wilhelm
• Lind Kurt
• Schroeder Friedrich
• Zimmermann Stefan

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5081 Primary

  Physics · mapped topic