Network device and information transmission method

US10031880B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10031880-B2
Application numberUS-201414565982-A
CountryUS
Kind codeB2
Filing dateDec 10, 2014
Priority dateDec 20, 2013
Publication dateJul 24, 2018
Grant dateJul 24, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a SerDes link, and is configured to transmit service data and control information of a port of the physical layer component. The processor controls the port of the physical layer component by using the control information of the port of the physical layer component. The network device transmits the service data and the control information by using the system bus, so that the service board does not need to set a CPU processing the control information, thereby expanding an interface flexibly, and reducing device complexity and hardware costs.

First claim

Opening claim text (preview).

What is claimed is: 1. A network device, comprising: a main control board, wherein the main control board comprises a processor and a switching chip; and a service board, wherein the service board comprises a physical layer component, and the physical layer component comprises a plurality of ports; wherein: the switching chip is connected to the physical layer component using a system bus; the system bus includes a serializer/deserializer (SerDes) link; the physical layer component is configured to separately insert, according to a predefined rule, first control information of a port of the plurality of ports obtained for the port through a first management data input/output (MDIO) interface of the port, into a corresponding first Ethernet packet of a plurality of first Ethernet packets received from the plurality of ports, to obtain a plurality of first inserted Ethernet packets, and multiplex the plurality of first inserted Ethernet packets to obtain a multiplexed first Ethernet packet; the system bus is configured to transmit the multiplexed first Ethernet packet from the physical layer component to the switching chip; the switching chip is configured to demultiplex the multiplexed first Ethernet packet to obtain the plurality of first inserted Ethernet packets, extract, according to the predefined rule, the first control information from each first inserted Ethernet packet to obtain the first control information of the plurality of ports, and separately input the first control information of the plurality of ports into second MDIO interfaces that are of the main control board and respectively corresponding to the plurality of ports, to save the first control information of the plurality of ports as saved first control information; and the processor is configured to control the plurality of ports using the saved first control information. 2. The network device according to claim 1 , wherein the physical layer component comprises a time division multiplexer, an interleaver, and each of the plurality of ports corresponds to an insertion processor; an insertion processor corresponding to the port is configured to insert, according to the predefined rule, first control information of the port obtained through the first MDIO interface of the port into the corresponding first Ethernet packet received from the port, to obtain the first inserted Ethernet packet of the port; the time division multiplexer is configured to perform time division multiplexing on the plurality of first inserted Ethernet packets concurrently transmitted; and the interleaver is configured to perform bit/byte interleaving processing on the plurality of first inserted Ethernet packets from the time division multiplexer to obtain the multiplexed first Ethernet packet. 3. The network device according to claim 1 , wherein the switching chip is further configured to separately insert, according to the predefined rule, second control information of the plurality of ports respectively obtained through the second MDIO interfaces into a plurality of second Ethernet packets to be sent to the physical layer component, to obtain a plurality of second inserted Ethernet packets; and multiplex the plurality of second inserted Ethernet packets to obtain a multiplexed second Ethernet packet; the system bus is further configured to transmit the multiplexed second Ethernet packet from the switching chip to the physical layer component; and the physical layer component is further configured to demultiplex the multiplexed second Ethernet packet, to obtain the multiple second inserted Ethernet packets; and extract, according to the predefined rule, the second control information from each second inserted Ethernet packet, to obtain the second control information of the plurality of ports; and separately input the second control information of the plurality of ports into first MDIO interfaces of the plurality of ports, to save the second control information of the plurality of ports. 4. The network device according to claim 3 , wherein the physical layer component is further configured to save the second control information of the plurality of ports to a first control register of the physical layer component as saved second control information; and the service board is configured to perform management control on the plurality of ports according to the saved second control information in the first control register. 5. The network device according to claim 1 , wherein the predefined rule comprises: a rule for inserting/extracting control information in an interframe gap of an Ethernet packet; or a rule for inserting/extracting control information in a preamble of an Ethernet packet; or a rule for inserting/extracting control information in an interframe gap and a preamble of an Ethernet packet. 6. The network device according to claim 1 , further comprising: a standby main control board configured to implement active-standby protection with the main control board, and operate when the main control board is faulty, wherein the standby main control board comprises a standby processor and a standby switching chip; wherein: the standby switching chip is connected to the physical layer component by a standby system bus; and the standby system bus includes a second SerDes link. 7. The network device according to claim 1 , wherein the physical layer component is configured to obtain the first control information of the plurality of ports from a first control register of the physical layer component through the first MDIO interfaces of the plurality of ports; the switching chip is configured to save the first control information of the plurality of ports to a second control register of the switching chip as saved first control information; and the processor is configured to adjust statuses of the plurality of ports by modifying the saved first control information in the second control register. 8. An information transmission method, used in a network device, wherein the network device comprises a main control board and a service board, the main control board comprises a processor and a switching chip, and the service board comprises a physical layer component; wherein the physical layer component comprises a plurality of ports, the switching chip is connected to the physical layer component by a system bus, and the system bus includes a serializer/deserializer (SerDes) link; and the information transmission method comprises: separately inserting, by the physical layer component according to a predefined rule, first control information of a port of the plurality of ports obtained for the port through a first management data input/output (MDIO) interface of the port into a corresponding first Ethernet packet of first Ethernet packets received from the plurality of ports, to obtain a plurality of first inserted Ethernet packets; multiplexing, by the physical layer component, the plurality of first inserted Ethernet packets to obtain a multiplexed first Ethernet packet; transmitting, by the physical layer component, the multiplexed first Ethernet packet to the switching chip using the system bus; receiving, by the switching chip, the multiplexed first Ethernet packet, demultiplexing the multiplexed first Ethernet packet, to obtain the plurality of first inserted Ethernet packets, and extracting the first control information from each first inserted Ethernet packet, to obtain the first control information of the plurality of ports; separately inputting, by the switching chip, the first control information of the plurality of ports into second MDIO interfaces that are of the main control board and respectively corresponding to the plurality of ports, to save the first control information

Assignees

Inventors

Classifications

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • Interconnection of switching modules · CPC title

  • Gigabit ethernet switching [GBPS] · CPC title

  • O-ring seal · CPC title

  • Multichannel or multilink protocols · CPC title

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Frequently asked questions

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What does patent US10031880B2 cover?
The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a SerDes link, and is configured to transmit servic…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/4282. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).