Method and apparatus for improving snooping performance in a multi-core multi-processor

Patent metadata

Field	Value
Publication number	US-10031848-B2
Application number	US-15303105-A
Country	US
Kind code	B2
Filing date	Jun 14, 2005
Priority date	Jun 14, 2005
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

First claim

What is claimed is:

1. A processor, comprising:
a first core;
a second core; and
a scheduler in a bridge to seek an address match from a first memory transaction from a first core to an existing memory transaction from a second core in an outgoing transaction queue, wherein when said first memory transaction is a read request and said existing memory transaction is a writeback, said scheduler cancels a shared tag update when said address match is found.

2. The processor of claim 1 , wherein said scheduler identifies said read request for retry when said address match is found.

3. The processor of claim 1 , wherein when said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback, said scheduler prevents said cross-snoop request from advancing to a pending state when said address match is found.

4. The processor of claim 1 , wherein when said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback, said scheduler identifies said cross-snoop request for retry when said address match is found.

5. The processor of claim 1 , wherein when said first memory transaction is a writeback and said existing memory transaction is a cross-snoop request, said scheduler prevents said cross-snoop request from issuing when said address match is found.

6. The processor of claim 1 , wherein when said first memory transaction is a writeback and said existing memory transaction is a cross-snoop request, said scheduler identifies said cross-snoop request for retry when said address match is found.

7. A method, comprising:
seeking an address match between an existing memory transaction from a second core in an outgoing transaction queue of a processor with a first memory transaction from a first core of the processor; and
identifying a conflict when said address match is found, wherein when said first memory transaction is a read request and said existing memory transaction is a writeback, and wherein said identifying includes marking said read request for a retry to the first core of the processor when said address match is found.

8. The method of claim 7 , wherein when said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback, and wherein said identifying includes marking said cross-snoop request for a retry when said address match is found.

9. The method of claim 7 , wherein when said first memory transaction is a writeback and said existing memory transaction is a cross-snoop request, and wherein said identifying includes marking said cross-snoop request for a retry when said address match is found.

10. A system, comprising:
a memory; and
a processor including a first core, a second core, and a scheduler in a bridge to seek an address match from a first memory transaction from a first core to an existing memory transaction from a second core in an outgoing transaction queue, wherein when said first memory transaction is a read request and said existing memory transaction is a writeback, and wherein said scheduler identifies said read request for retry to the first core of the processor when said address match is found.

11. The system of claim 10 , wherein when said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback, and wherein said scheduler identifies said cross-snoop request for retry when said address match is found.

12. The system of claim 10 , wherein when the first memory transaction is a writeback and said existing memory transaction is a cross-snoop request, and wherein said scheduler identifies said cross-snoop request for retry when said address match is found.

Assignees

• Sistla Krishnakanth V
• Liu Yen Cheng
• Cai Zhong Ning
• Intel Corp

Inventors

• Sistla Krishnakanth V
• Liu Yen-Cheng
• Cai Zhong-Ning

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title