Method of and circuit for generating a physically unclonable function

Patent metadata

Field	Value
Publication number	US-10027492-B1
Application number	US-201715633321-A
Country	US
Kind code	B1
Filing date	Jun 26, 2017
Priority date	Jun 26, 2017
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A method of generating a physically unclonable function is described. The method comprises calculating a total variation associated with differences between a plurality of elements of an entropy source in an integrated circuit; calculating a global variation associated the plurality of elements of the entropy source; generating a local variation by removing the global variation associated with the plurality of elements from the total variation; and generating a unique signature based upon the generated local variation. A circuit for generating a physically unclonable function is also described.

First claim

What is claimed is:

1. A method of generating a physically unclonable function, the method comprising:
calculating a total variation associated with differences between a plurality of elements of an entropy source in an integrated circuit;
calculating a global variation associated with the plurality of elements of the entropy source;
generating a local variation by removing the global variation associated with the plurality of elements from the total variation; and
generating a unique signature based upon the generated local variation.

2. The method of claim 1 wherein calculating a total variation associated with differences between the plurality of elements of an entropy source comprises calculating measurable differences due to manufacturing variations in the integrated circuit.

3. The method of claim 1 wherein calculating a total variation associated with differences between a plurality of elements of an entropy source comprises generating a vector representing the differences between the plurality of elements of the entropy source.

4. The method of claim 3 wherein calculating a global variation comprises generating a vector representing a global gradient.

5. The method of claim 4 wherein the vector representing a global gradient comprises directional and magnitude values.

6. The method of claim 4 further comprising generating a gradient magnitude associated with the global gradient, wherein generating a local variation comprises subtracting, for each vector component of the vector representing the differences between the plurality of elements of the entropy source, the gradient magnitude from the vector component.

7. The method of claim 1 wherein the plurality of elements of the entropy source comprises a plurality of ring oscillators at predetermined locations of the integrated circuit device.

8. The method of claim 7 wherein calculating a total variation comprises generating a vector representing the differences between the plurality of ring oscillators.

9. The method of claim 8 wherein calculating a global variation comprises generating a vector representing a global gradient.

10. The method of claim 9 further comprising generating a gradient magnitude associated with the global gradient, wherein generating a local variation comprises subtracting, for each vector component of the vector representing the differences between the plurality of ring oscillators, the gradient magnitude from the vector component.

11. A circuit for generating a physically unclonable function, the circuit comprising:
a plurality of elements of an entropy source in an integrated circuit; and
a processor of the integrated circuit configured to calculate a total variation associated with differences between the plurality of elements of the entropy source and to calculate a global variation associated the plurality of elements of the entropy source;
wherein the processor generates a local variation by removing the global variation associated with the plurality of elements from the total variation, and generates a unique signature based upon the generated local variation.

12. The circuit of claim 11 wherein the processor calculates a total variation associated with differences between the plurality of elements of the entropy source by calculating measurable differences due to manufacturing variations is the integrated circuit.

13. The circuit of claim 11 wherein the processor calculates a total variation associated with differences between the plurality of elements of the entropy source by generating a vector representing the differences between the plurality of elements of the entropy source.

14. The circuit of claim 13 wherein the processor calculates a global variation by generating a vector representing a global gradient.

15. The circuit of claim 14 wherein the vector representing a global gradient comprises directional and magnitude values.

16. The circuit of claim 14 wherein the processor further generates a gradient magnitude associated with the global gradient, wherein the local variation is generated by subtracting, for each vector component of the vector representing the differences between the plurality of elements of the entropy source, the gradient magnitude from the vector component.

17. The circuit of claim 11 wherein the plurality of elements of the entropy source comprises a plurality of ring oscillators at predetermined locations of the integrated circuit device.

18. The circuit of claim 17 wherein the processor calculates a total variation associated with differences between the plurality of elements of the entropy source by generating a vector representing the differences between the plurality of ring oscillators.

19. The circuit of claim 18 wherein the processor calculates a global variation by generating a vector representing a global gradient.

20. The circuit of claim 19 the processor further generates a gradient magnitude associated with the global gradient, wherein a local variation is generated by subtracting, for each vector component of the vector representing the differences between the plurality of ring oscillators, the gradient magnitude from the vector component.

Assignees

• Xilinx Inc

Inventors

• Wesselkamper James D

Classifications

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G11C11/41

  forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger · CPC title