PWM modulator

Patent metadata

Field	Value
Publication number	US-10027315-B2
Application number	US-201715431374-A
Country	US
Kind code	B2
Filing date	Feb 13, 2017
Priority date	Jan 17, 2014
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.

First claim

What is claimed is:

1. A method, comprising:
generating, using an integrator of a pulse width modulation (PWM) modulator, a triangular waveform based at least on a square wave carrier signal received at an input node of the integrator; and
generating a synchronous peak at one or more vertexes of the triangular waveform by injecting, into the input node of the integrator, a derivative signal of an auxiliary clock signal, wherein the auxiliary clock signal is configured to have a phase lead with respect to a clock signal of a circuit configured to generate the square wave carrier signal.

2. The method of claim 1 , wherein generating the synchronous peak at one or more vertexes of the triangular waveform comprises shifting a downward slope of the triangular waveform and an upward slope of the triangular waveform in opposite directions.

3. The method of claim 1 , wherein the synchronous peak at one or more vertexes of the triangular waveform is configured to reduce pulse skipping caused by a characteristic affecting a modulating signal received at the input node of the integrator and configured to modulate the square wave carrier signal.

4. The method of claim 3 , wherein the characteristic comprises a disturbance or an oscillation of the modulating signal.

5. A method, comprising:
generating, by a circuit comprising a high pass filter, a derivative signal of a first clock signal;
generating, using an integrator, a triangular waveform based on the derivative signal, a modulating signal, and a square wave carrier signal received at an input node of the integrator; and
comparing the triangular waveform against a threshold.

6. The method of claim 5 , wherein a frequency of the square wave carrier signal is greater than a frequency of the modulating signal.

7. The method of claim 6 , further comprising generating, using a square wave generator clocked by a second clock signal, the square wave carrier signal, wherein the first clock signal is configured to have a phase lead with respect to the second clock signal.

8. The method of claim 7 , wherein the derivative signal is characterized by consecutive spikes separated by a time interval indicative of the phase lead.

9. The method of claim 5 , wherein generating the triangular waveform comprises creating a synchronous peak at vertexes of the triangular waveform based on the derivative signal.

10. The method of claim 9 , wherein creating the synchronous peak comprises shifting a downward slope and an upward slope of the triangular waveform in opposite directions.

11. The method of claim 5 , further comprising generating a pulse-width modulated square wave carrier signal based on the comparing.

12. A method, comprising:
receiving, at an input node of an integrator, a modulating signal and a square wave carrier signal, the square wave carrier signal having a frequency greater than a frequency of the modulating signal;
generating an auxiliary clock signal having a phase lead with respect to a clock signal associated with the square wave carrier signal;
generating, by a circuit comprising a logic gate, a derivative signal of the auxiliary clock signal;
generating, by the integrator, a triangular waveform based on the derivative signal, the modulating signal, and the square wave signal received at the input node of the integrator; and
comparing, by a comparator, the triangular waveform with a fixed threshold.

13. The method of claim 12 , further comprising generating, by the comparator, a pulse width modulated square wave carrier signal based on the comparing.

14. The method of claim 12 , wherein the integrator has a drain output configuration.

15. The method of claim 12 , generating the triangular waveform comprises generating synchronous peak at one or more vertexes of the triangular waveform.

16. The method of claim 15 , wherein generating synchronous peaks at one or more vertexes of the triangular waveform comprises shifting a downward slope of the triangular waveform and an upward slope of the triangular waveform in opposite directions.

17. The method of claim 15 , wherein the synchronous peak at one or more vertexes of the triangular waveform is configured to reduce pulse skipping caused by an oscillation affecting the modulating signal received at the input node of the integrator.

18. The method of claim 12 , wherein the circuit further comprises a high pass filter.

19. The method of claim 1 , wherein the auxiliary clock signal is distinct from the square wave carrier signal and the triangular waveform.

Assignees

• St Microelectronics Srl

Inventors

• Raimondi Marco
• Botti Edoardo

Classifications

• H03K5/12

  by steepening leading or trailing edges · CPC title

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F1/32

  Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03K4/08

  having sawtooth shape · CPC title