Integrated circuit

Patent metadata

Field	Value
Publication number	US-10027282-B2
Application number	US-201615387755-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Apr 20, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 μm to 1 mm, a width of the at least one line is ⅓ or less of a width of the first plane, and a pattern ratio is 1 or more.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a first amplifier stage;
a second amplifier stage;
a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other;
a first plane for ground connected to the first amplifier stage;
a second plane for ground connected to the second amplifier stage; and
at least one line for ground connecting the first plane and the second plane to each other, the at least one line being disposed to overlap the first signal line,
wherein the at least one line has a center line having a length of 10 μm to 1 mm, a width of the at least one line is ⅓ or less of a width of the first plane, and a pattern ratio which is a value obtained by dividing the length of the center line by the width of the at least one line is 1 or more.

2. The integrated circuit according to claim 1 , wherein the first amplifier stage and the second amplifier stage include a single-phase input and a single-phase output each.

3. The integrated circuit according to claim 1 , further comprising:
a semiconductor substrate having a surface on which the first amplifier stage, the second amplifier stage, and the first signal line are formed;
a dielectric film disposed between the first amplifier stage, the second amplifier stage and the first signal line and the first plane and the second plane;
a first connection structure connecting the first amplifier stage and the first plane to each other; and
a second connection structure connecting the second amplifier stage and the second plane to each other.

4. The integrated circuit according to claim 3 , wherein the first plane and the second plane are disposed on the dielectric film and on an uppermost surface side of the semiconductor substrate to cover the first amplifier stage and the second amplifier stage.

5. The integrated circuit according to claim 1 ,
wherein
a dielectric film is disposed between the at least one line and the first signal line, and
the at least one line, the dielectric film, and the first signal line form a first micro-strip line.

6. The integrated circuit according to claim 1 , wherein the at least one line includes a first spiral inductor.

7. The integrated circuit according to claim 1 , wherein the at least one line includes a first resistive device having a resistance of 10Ω or more.

Assignees

• Mitsubishi Electric Corp

Inventors

• Sugitani Takumi
• Kurusu Hitoshi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title