Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component

US10026868B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10026868-B2
Application numberUS-201515508899-A
CountryUS
Kind codeB2
Filing dateSep 2, 2015
Priority dateSep 4, 2014
Publication dateJul 17, 2018
Grant dateJul 17, 2018

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23), and —a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein —the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that —the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and —the first contact layer (41) and the second contact layer (42) run parallel to each other.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing an optoelectronic semiconductor component, comprising the following steps: A) provision of a patterned semiconductor layer sequence comprising a one-piece first semiconductor layer with a bottom face, a main plane of extension, at least one recess, in particular a multiplicity of recesses, and a first top face remote from the bottom face in the region of the recesses, an active layer, and a second semiconductor layer at a side of the active layer remote from the first semiconductor layer, wherein the active layer and the second semiconductor layer are jointly patterned and, together with the first semiconductor layer, form at least one emission region; and B) simultaneous application of a first contact layer to the first top face and of a second contact layer to the second top face, remote from the first semiconductor layer, of the at least one emission region, wherein the first contact layer and the second contact layer are electrically separated from one another, wherein the first contact layer and the second contact layer extend within the bounds of manufacturing tolerances parallel to one another and to the main plane of extension, wherein no passivation layer is used during the production process, whereby the first top face is exposed prior to application of the first contact layer, and the first top face is completely covered with the first contact layer, wherein the first contact layer is of one-piece configuration and in each case encloses the emission regions in a manner of a frame, and wherein the second contact layer is of multi-piece configuration, and a one-piece region of the second contact layer is associated on a one-to-one basis with each emission region. 2. The method according to claim 1 , wherein the first contact layer and the second contact layer are deposited by means of a directional deposition method. 3. The method according to claim 1 , wherein the active layer and the second semiconductor layer are patterned into a multiplicity of laterally mutually spaced regions, and each region, together with the first semiconductor layer, forms an emission region. 4. The method according to claim 1 , wherein, after step B), the as yet unfinished optoelectronic semiconductor component is immersed in an acid bath for a predeterminable interval of time, such that traces of the material of the first contact layer and of the second contact layer are removed from the side faces of the emission regions. 5. The method according to claim 1 , wherein after step B) the following method steps are carried out: C) whole-surface application of a first insulation layer on exposed outer faces remote from the first semiconductor layer; D) partial removal of the first insulation layer in the region of second contact faces, remote from the emission regions, of the second contact layer; and E) application of metallization to the regions of the second contact faces at which the first insulation layer has been removed. 6. The method according to claim 5 , wherein after step E) the following method steps are carried out: F) application of a second insulation layer which, together with the first insulation layer, forms a dielectric, such that the dielectric completely fills the recesses and projects vertically beyond the metallization; and G) removal of the dielectric such that metal faces of the metallization remote from the first semiconductor layer terminate flush with end faces of the dielectric remote from the first semiconductor layer. 7. The method according to claim 1 , wherein all of the side faces, extending transversely of the main plane of extension, of the at least one emission region and/or of the active layer are free of the first contact layer and of the second contact layer. 8. An optoelectronic semiconductor component, comprising: a patterned semiconductor layer sequence comprising a one-piece first semiconductor layer with a bottom face, a main plane of extension, at least one recess, in particular a multiplicity of recesses, and a first top face remote from the bottom face in the region of the recesses, an active layer, and a second semiconductor layer at a side of the active layer remote from the first semiconductor layer, wherein the active layer and the second semiconductor layer are jointly patterned into regions, in particular into a multiplicity of laterally mutually spaced regions, and each region, together with the first semiconductor layer, forms an emission region; a first contact layer, which is applied to the first top face; and a second contact layer, which is applied to a second top face, remote from the bottom face, of the emission regions, wherein the first contact layer and the second contact layer are not connected together electrically conductively, extend parallel to one another and to the main plane of extension within the bounds of manufacturing tolerances, have the same thickness and are formed from the same material, wherein the first top face of the first semiconductor layer is completely covered by the first contact layer, wherein the first contact layer is of one-piece configuration and in each case encloses the emission regions in a manner of a frame, and wherein the second contact layer is of multi-piece configuration, and a one-piece region of the second contact layer is associated on a one-to-one basis with each emission region. 9. The optoelectronic semiconductor component according to claim 8 , wherein the side faces of the emission regions exhibit traces of the material of the first contact layer and of the second contact layer. 10. The optoelectronic semiconductor component according to claim 8 , wherein the first contact layer and the second contact layer appear as a continuous metal layer in plan view from a side remote from the bottom face of the first semiconductor layer. 11. The optoelectronic semiconductor component according to claim 8 , wherein metallization with metal faces remote from the first semiconductor layer is applied to the second contact layer, wherein the metallization is of multi-piece configuration, and a one-piece region of the metallization is associated on a one-to-one basis with each emission region, and wherein each one-piece region of the metallization has a smaller lateral extent than the emission region associated therewith on a one-to-one basis. 12. The optoelectronic semiconductor component according to claim 11 , wherein a dielectric is arranged between the emission regions, wherein the metal faces of the metallization terminate flush with end faces of the dielectric remote from the first semiconductor layer, wherein the dielectric completely covers the first contact layer at the side thereof remote from the first semiconductor layer, and wherein the dielectric completely covers the second contact layer at points which are not covered by the metallization. 13. The optoelectronic semiconductor component according to claim 8 , wherein the first top face of the first semiconductor layer is covered in places by the dielectric, and wherein the regions of the second contact layer project laterally in places beyond the respectively associated emission region. 14. The optoelectronic semiconductor component according to claim 8 , wherein all of the side faces, extending transversely of the main plane of extension, of the at least one emission region and/or of the active layer are free of the first contact layer and of the second contact layer. 15. An optoelectronic semiconductor component, comprising: a patterned semiconductor layer sequence comprising a one

Assignees

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Classifications

  • of Group IV materials · CPC title

  • of insulating materials · CPC title

  • Etching of wafers, substrates or parts of devices · CPC title

  • of electrodes ohmically coupled to a semiconductor · CPC title

  • Package configurations · CPC title

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What does patent US10026868B2 cover?
A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23),…
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh
What technology area does this patent fall under?
Primary CPC classification H01L33/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).