Memory devices using etching stop layers

Patent metadata

Field	Value
Publication number	US-10026746-B2
Application number	US-201715604028-A
Country	US
Kind code	B2
Filing date	May 24, 2017
Priority date	Oct 14, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

First claim

What is claimed is:

1. A memory device comprising:
a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate;
a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and
a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively,
wherein respective ones of the etching stop layers comprise an air gap therein.

2. The memory device as claimed in claim 1 , wherein respective ones of the etching stop layers comprise a lateral surface contacting respective ones of the insulating layers and an upper surface and a lower surface extending from the lateral surface.

3. The memory device as claimed in claim 1 , wherein the etching stop layers are formed of silicon carbon nitride (SiCN) and/or silicon oxynitride (SiON).

4. The memory device as claimed in claim 1 , further comprising: a filling layer in at least a portion of the etching stop layers.

5. The memory device as claimed in claim 4 , wherein the air gap is formed in the filling layer.

6. The memory device as claimed in claim 4 , wherein the filling layer comprises a high-k dielectric material.

7. The memory device as claimed in claim 4 , wherein the filling layer comprises a plurality of layers formed of different materials, at least one of the plurality of layers comprising a conductive material.

8. The memory device as claimed in claim 1 , further comprising a plurality of channel structures passing through the gate structure and extending in a direction substantially perpendicular to an upper surface of the substrate.

9. The memory device as claimed in claim 1 , wherein a portion of one of the plurality of etching stop layers comes in contact with at least one of the contacts.

10. A memory device comprising:
a plurality of gate electrode layers having a pad region connected to respective ones of a plurality of contacts; and
a plurality of gate isolating layers alternately stacked with the gate electrode layers, and comprising a first region and a second region formed of different materials, respectively,
wherein the second region of respective ones of the gate isolating layers is on a lower portion of the pad region of respective ones of the gate electrode layers, and comprises a plurality of layers formed of different materials under the respective ones of the gate electrode layers.

11. The memory device as claimed in claim 10 , wherein the plurality of layers comprise:
an etching stop layer on a lateral surface of the second region contacting the first region and on an upper surface and a lower surface of the second region; and
at least one filling layer inside the etching stop layer.

12. The memory device as claimed in claim 11 , wherein the etching stop layer comprises silicon carbon nitride (SiCN) and/or silicon oxynitride (SiON).

13. The memory device as claimed in claim 11 , wherein the at least one filling layer comprises a high-k dielectric material.

14. The memory device as claimed in claim 13 , further comprising:
blocking layers surrounding the plurality of gate electrode layers, respectively,
wherein the at least one filling layer comprises the same high-k dielectric material as the blocking layers.

15. The memory device as claimed in claim 11 , wherein an interior of the etching stop layer is filled with the at least one filling layer.

16. A memory device comprising:
a substrate;
a gate electrode layer on the substrate and extending in a first direction substantially parallel to an upper surface of the substrate;
a contact on the gate electrode layer and extending in a second direction crossing the first direction, wherein the contact penetrates into at least a portion of the gate electrode layer;
an insulating layer adjacent the gate electrode layer and between the gate electrode layer and the substrate; and
an etching stop layer adjacent the insulating layer and between the contact and the substrate,
wherein the etching stop layer comprises an upper segment and a lower segment,
wherein the upper segment is adjacent the gate electrode layer, and
wherein the lower segment is separated from the upper segment in the second direction.

17. The memory device as claimed in claim 16 , further comprising at least one filling layer between the upper segment and the lower segment of the etching stop layer.

18. The memory device as claimed in claim 17 , wherein the at least one filling layer comprises a first filling layer and a second filling layer, and
wherein the first filling layer comprises a first material different from a second material of the second filling layer.

19. The memory device as claimed in claim 18 , wherein the first material is a high-k dielectric material, and
wherein the second material is a conductive material.

20. The memory device as claimed in claim 16 , further comprising an air gap between the upper segment and the lower segment of the etching stop layer.

Assignees

• Lee Jeong Gil
• Kim Jee Yong
• Lee Jung Hwan
• Byeon Dae Seok
• Lim Hyun Seok
• Samsung Electronics Co Ltd

Inventors

• Lee Jeong Gil
• Kim Jee Yong
• Lee Jung Hwan
• Byeon Dae Seok
• Lim Hyun Seok

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title