Decoupling capacitor with metal programmable knee frequency

Patent metadata

Field	Value
Publication number	US-10026735-B2
Application number	US-201615360777-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Nov 23, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.

First claim

What is claimed is:

1. A metal oxide semiconductor (MOS) integrated circuit (IC), the MOS integrated circuit comprising:
a first plurality of MOS transistors, each having a transistor drain, a transistor source, and a transistor gate, each transistor gate of the first plurality of MOS transistors extending in a first direction and being coupled to other transistor gates of the first plurality of MOS transistors, each transistor source and each transistor drain of the first plurality of MOS transistors being coupled to a first voltage source; and
a first metal interconnect and a second metal interconnect extending over the first plurality of MOS transistors, the first metal interconnect having a first end and a second end, the first metal interconnect being coupled to each transistor gate of the first plurality of MOS transistors and being coupled to a second voltage source, one of each transistor gate of the first plurality of MOS transistors or the second voltage source being coupled to the first metal interconnect through at least one tap point located between the first end and the second end to adjust a resistance of the plurality of MOS transistors, the second metal interconnect being coupled to each transistor source and each transistor drain of the first plurality of MOS transistors, the second metal interconnect having portions that extend between portions of the first metal interconnect to increase a capacitance of the plurality of MOS transistors, the first plurality of MOS transistors functioning as a decoupling capacitor.

2. The MOS IC of claim 1 , wherein the first metal interconnect extends in the first direction over the first plurality of MOS transistors, and in a second direction orthogonal to the first direction over the first plurality of MOS transistors.

3. The MOS IC of claim 1 , further comprising a second plurality of MOS transistors, each having a transistor drain, a transistor source, and a transistor gate, each transistor gate of the second plurality of MOS transistors extending in the first direction and being coupled together, each transistor source and each transistor drain of the second plurality of MOS transistors being coupled to the first voltage source, each transistor gate of the second plurality of MOS transistors and a corresponding transistor gate of the first plurality of MOS transistors being formed through a gate interconnect extending in the first direction.

4. The MOS IC of claim 3 , wherein the first metal interconnect is coupled to each transistor gate of the first and second plurality of MOS transistors at one of the first end or the at least one tap point between the first end and the second end, the first metal interconnect is coupled to the second voltage source at an other of the first end or the at least one tap point between the first end and the second end, and the first metal interconnect extends over the second plurality of MOS transistors.

5. The MOS IC of claim 4 , wherein the first end is coupled to the transistor gates of the first plurality of MOS transistors and the second plurality of MOS transistors, and the at least one tap point is coupled to the second voltage source.

6. The MOS IC of claim 5 , wherein the second end is unconnected.

7. The MOS IC of claim 4 , further comprising:
a third plurality of MOS transistors, each having a transistor drain, a transistor source, and a transistor gate, each transistor gate of the third plurality of MOS transistors extending in the first direction and being coupled to other transistor gates of the third plurality of MOS transistors, each transistor source and each transistor drain of the third plurality of MOS transistors being coupled to the first voltage source; and
a fourth plurality of MOS transistors, each having a transistor drain, a transistor source, and a transistor gate, each transistor gate of the fourth plurality of MOS transistors extending in the first direction and being coupled together, each transistor source and each transistor drain of the fourth plurality of MOS transistors being coupled to the first voltage source, each transistor gate of the fourth plurality of MOS transistors and a corresponding transistor gate of the third plurality of MOS transistors being formed through a gate interconnect extending in the first direction, wherein the first metal interconnect is coupled to each transistor gate of the third and fourth plurality of MOS transistors at one of the first end or the at least one tap point between the first end and the second end, and the first metal interconnect extends over the third and fourth plurality of MOS transistors.

8. The MOS IC of claim 3 , wherein the first metal interconnect extends in the first direction over the first plurality of MOS transistors and the second plurality of MOS transistors, and in a second direction orthogonal to the first direction, over the plurality of MOS transistors and the second plurality of MOS transistors.

9. The MOS IC of claim 3 , further comprising:
the second metal interconnect extending in a second direction orthogonal to the first direction, the second metal interconnect being coupled to each transistor source and each transistor drain of the first plurality of MOS transistors and being coupled to the first voltage source; and
a third metal interconnect extending in the second direction, the third metal interconnect being coupled to each transistor source and each transistor drain of the second plurality of MOS transistors and being coupled to the first voltage source.

10. The MOS IC of claim 1 , wherein the first metal interconnect and the second metal interconnect are located on a metal one (M1) layer.

11. The MOS IC of claim 9 , wherein the first metal interconnect extends in the first direction, and in the second direction orthogonal to the first direction, over the first plurality of MOS transistors and the second plurality of MOS transistors and between the second metal interconnect and the third metal interconnect.

12. The MOS IC of claim 11 , wherein the second metal interconnect and the third metal interconnect include portions that extend in the first direction and that extend between portions of the first metal interconnect that extend in the first direction.

13. The MOS IC of claim 3 , wherein the first metal interconnect extends in one of the first direction or a second direction over the transistor sources of the first plurality of MOS transistors and the second plurality of MOS transistors, and in an other of the first direction or the second direction over the transistor drains of the first plurality of MOS transistors and the second plurality of MOS transistors, the second direction being orthogonal to the first direction.

14. The MOS IC of claim 13 , wherein the first metal interconnect extends in the first direction over the transistor sources of the first plurality of MOS transistors and the second plurality of MOS transistors, and in the second direction over the transistor drains of the first plurality of MOS transistors and the second plurality of MOS transistors.

15. The MOS IC of claim 1 , wherein the first plurality of MOS transistors and the first metal interconnect are located in a gutter region adjacent to one of a processor or a controller of the MOS IC.

16. The MOS IC of claim 1 , wherein the first plurality of MOS transistors and the first metal interconnect function as a decoupling capacitor having a knee frequency that is a function of the at least one tap point.

17. A method of operation of a metal oxide semiconductor (MOS) integrated circuit (IC) decoupling capacitor, compr

Assignees

• Qualcomm Inc

Inventors

• Zhao andi
• Vilangudipitchai Ramaprasath
• Kumar Dorav

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title

• H01L27/088 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic