Decoupling capacitors and arrangements

Patent metadata

Field	Value
Publication number	US-10026686-B2
Application number	US-201415125964-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A transistor assembly, comprising:
a base layer in which a transistor is included, wherein the transistor has a supply line;
a first metal layer;
a second metal layer between the base layer and the first metal layer; and
a capacitor, comprising a sheet of conductive material having a channel therein, wherein the capacitor is in the base layer or the second metal layer, wherein the capacitor is coupled to the supply line of the transistor, wherein the capacitor is substantially planar and has interleaved fingers spaced apart by the channel, and wherein the interleaved fingers include a first set of interleaved fingers that form a first capacitor plate and a second set of interleaved fingers that form a second capacitor plate.

2. The transistor assembly of claim 1 , wherein:
the first metal layer is an outermost metal layer of a die; and
the capacitor is closer to the base layer than to the first metal layer.

3. The transistor assembly of claim 1 , wherein the capacitor is coupled to a voltage supply of the transistor assembly.

4. The transistor assembly of claim 1 , wherein the capacitor is in the base layer.

5. The transistor assembly of claim 1 , wherein the transistor is a tri-gate transistor.

6. The transistor assembly of claim 1 , wherein the capacitor is entirely in the second metal layer, and wherein the second metal layer is a metal layer closest to the base layer.

7. The transistor assembly of claim 1 , wherein the capacitor is substantially planar and has interleaved fingers spaced apart by the channel.

8. The transistor assembly of claim 1 , wherein the conductive material is metal.

9. The transistor assembly of claim 1 , wherein the capacitor is in the second metal layer and over the transistor.

10. An integrated circuit (IC) device, comprising:
a transistor assembly, comprising:
a base layer in which a transistor is included, wherein the transistor has a supply line,
a first metal layer,
a second metal layer between the base layer and the first metal layer, and
a capacitor comprising a sheet of conductive material having a channel therein, wherein the capacitor is in the second metal layer and over the transistor; and

a voltage supply;
wherein the capacitor is coupled to the voltage supply and to the transistor supply line.

11. The IC device of claim 10 , wherein the capacitor is in the base layer.

12. The IC device of claim 10 , wherein the transistor is a tri-gate transistor.

13. The IC device of claim 10 , wherein the transistor is a driver transistor, and wherein the base layer further comprises a plurality of load transistors coupled to the driver transistor.

14. The IC device of claim 10 , wherein the second metal layer is a metal layer closest to the base layer.

15. A method of forming a transistor assembly, comprising:
forming a transistor in a base layer on a substrate, wherein the transistor has a supply line;
forming a capacitor in the base layer or a second metal layer by selectively patterning a sheet of conductive material to form a channel in the sheet of conductive material, wherein the capacitor is substantially planar and has interleaved fingers spaced apart by the channel, and wherein the interleaved fingers include a first set of interleaved fingers that form a first capacitor plate and a second set of interleaved fingers that form a second capacitor plate;
coupling the capacitor to the transistor supply line; and
forming a first metal layer such that the capacitor is disposed between the substrate and the first metal layer.

16. The method of claim 15 , wherein the conductive material is metal.

17. The method of claim 15 , wherein selectively patterning the conductive sheet comprises using an electron beam direct write technique.

18. The method of claim 15 , wherein selectively patterning the conductive sheet comprises using an extreme ultraviolet lithography technique.

19. The method of claim 15 , wherein forming the capacitor in the base layer or the second metal layer is performed prior to forming the first metal layer.

20. The method of claim 15 , wherein forming the transistor comprises forming a tri-gate transistor.

21. The method of claim 15 , wherein forming the capacitor in the base layer or the second metal layer comprises forming a plurality of capacitors in the base layer or the second metal layer.

Assignees

• Intel Corp

Inventors

• Bou-Ghazale Silvio E
• Elsayed Rany T
• Goel Niti

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H01L28/88

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic