Semiconductor device for testing large number of devices and composing method and test method thereof

Patent metadata

Field	Value
Publication number	US-10026661-B2
Application number	US-201514844398-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Sep 18, 2014
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.

First claim

What is claimed is:

1. A method for forming a semiconductor device for test, comprising:
performing a Front End of Line (FEOL) process that includes forming a plurality of elements or a plurality of logic cells including vias and metal lines at an upper layer portion on a plurality of transistors including gates;
forming a selection logic for selecting at least one of the plurality of transistors, using at least one of the plurality of elements or the plurality of logic cells;
connecting the selection logic and the plurality of transistors;
forming a pad for connecting an input terminal of the selection logic and the gates of the plurality of transistors, wherein
the selection logic is configured to select the at least one of the plurality of transistors by turning on the at least one of the plurality of transistors while unselected transistors among the plurality of transistors are turned off, and
the forming the selection logic includes removing the vias and metal lines formed at the upper layer portion of the plurality of elements or the plurality of logic cells formed at the semiconductor device after the FEOL process is performed.

2. The method of claim 1 , wherein the plurality of elements are elements placed at a specific chip area of the semiconductor device.

3. The method of claim 1 , wherein the plurality of logic cells are standard logic cells at the semiconductor device.

4. The method of claim 1 , wherein
the plurality of logic cells include logic filler cells that are cells assigned to filler cells at a design level of the semiconductor device, and
the logic filler cells are formed to have the same function of a standard logic cell.

5. The method of claim 4 , wherein
the logic filler cells and the standard logic cells each include input and output terminals,
the FEOL process of the forming the plurality of elements or the plurality of logic cells includes forming the input and output terminals of the logic filler cells so they are separated from the input and output terminals of standard logic cells.

6. The method of claim 1 , wherein the selection logic is implemented with a decoder intellectual property (IP) formed at a specific chip area according to locations of the plurality of transistors at a design level of the semiconductor device.

7. The method of claim 1 , wherein the forming the selection logic includes routing a decoder circuit previously formed for a specific function at the semiconductor device.

8. The method of claim 1 , further comprising:
forming a contact or a conductive line for forming the selection logic after the removing the vias and the metal lines.

9. A method for forming a semiconductor device for test, comprising:
forming transistors and at least one of elements, logic cells, and intellectual properties (IPs) for the semiconductor device for test using a FEOL process, the transistors including gates, drains, and sources;
forming a decoder for sequentially selecting the transistors in response to a selection signal, the forming the decoder including one of,
selecting one of standard cells or elements corresponding to positions where minimum conductive lines are needed when forming the decoder, and forming the decoder from the selected one of the standard cells or elements, and
selecting one of the standard cells or elements that has a size larger than a reference size and modifying the selected one of the standard cells or elements into the decoder;

connecting the decoder to the transistors; and
forming a pad for connecting an input terminal of the decoder to the gates of the transistors.

10. The method of claim 9 , further comprising:
disposing at least one of elements, logic cells, and intellectual properties (IPs) for forming a decoder at a chip area of the semiconductor device for test, wherein
the disposing the transistors and the at least one of elements, logic cells, and intellectual properties (IPs) includes selecting an element or logic cell configured to perform a specific function among the elements or the logic cells.

11. The method of claim 9 , wherein the forming the decoder includes the selecting one of the standard cells or elements corresponding to positions where minimum conductive lines are needed when forming the decoder, and forming the decoder from the selected one of the standard cells or elements.

12. The method of claim 9 , wherein the forming the decoder includes the selecting one of the standard cells or elements that has a size larger than a reference size and modifying the selected one of the standard cells or elements into the decoder.

13. The method of claim 9 , further comprising:
disposing at least one of elements, logic cells, and intellectual properties (IPs) for forming a decoder at a chip area of the semiconductor device for test, wherein
the disposing includes deciding a number, locations, and a decoding size of the IPs according to the pad and a number of transistors or locations of the pad and the transistors.

14. The method of claim 9 , further comprising:
removing vias or metal lines after the FEOL process.

15. A method for testing target transistors on a Front End of Line (FEOL)-end-semiconductor device, the FEOL-end-semiconductor device including the target transistors and at least one of a plurality of elements and a plurality of logic cells formed using a FEOL process, the target transistors each including a source, a gate, and a drain, the method comprising:
forming a decoder by modifying the at least one of the plurality of elements and the plurality of logic cells on the FEOL-end-semiconductor device;
forming a pad pattern, the pad pattern defining an input terminal connected to the decoder, a source terminal connected to a source of at least one of the target transistors, and a drain terminal connected to a drain of at least one of the target transistors;
connecting the decoder to the gates of the target transistors;
selecting a selected target transistor among the target transistors using the decoder, the selecting the selected target transistor including turning the selected target transistor on while unselected target transistors among the target transistors are turned off, and
measuring an electrical characteristic of the selected target transistor using the source terminal and the drain terminal, wherein
the at least one of the plurality of elements and the plurality of logic cells on the FEOL-end-semiconductor device are connected to vias and metal lines, and the forming the decoder includes removing the vias and the metal lines connected to the at least one of the plurality of elements and the plurality of logic cells on the FEOL-end-semiconductor device and routing a new interconnection structure to the at least one of the plurality of elements and the plurality of logic cells being modified into the decoder, or
the FEOL-end-semiconductor device includes a circuit block divided into a plurality of rows on a basis of power rails,
each of the rows includes standard logic cells, logic filler cells, and general filler cells, the forming the decoder includes modifying one of the logic filler cells into the decoder, and
the connecting the decoder to the gates of the target transistors includes connecting the decoder to gates of the standard logic cells in a same row as the decoder.

16. The method of claim 15 , wherein
the sources of the target transistors are connected to a common source,
the drains of the target transistors are connected to a common drain, and
the forming the pad pattern includes forming the source terminal connected to the common source and fo

Assignees

• Won Hyosig
• Hyun Daijoon
• Jeong Kwangok
• Samsung Electronics Co Ltd

Inventors

• Won Hyosig
• Hyun Daijoon
• Jeong Kwangok

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title