Multilayer capacitor and board having the same mounted thereon

US10026558B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10026558-B1
Application numberUS-201815879100-A
CountryUS
Kind codeB1
Filing dateJan 24, 2018
Priority dateApr 11, 2017
Publication dateJul 17, 2018
Grant dateJul 17, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A multilayer capacitor includes a capacitor body including a dielectric layer and a first internal electrode and a second internal electrode; a first via electrode exposed through first and second surfaces of the capacitor body, connected to the first internal electrode and spaced apart from the second internal electrode, a second via electrode exposed through the first and second surfaces of the capacitor body, and connected to the second internal electrode and spaced apart from the first internal electrode, a first and second external electrodes disposed on the first surface of the capacitor body to be spaced apart from each other, and connected to the first and the second via electrodes, respectively, and first and second covers disposed in sequence from a bottom in the second surface of the capacitor body, wherein the first and second cover are formed of different materials.

First claim

Opening claim text (preview).

What is claimed is: 1. A multilayer capacitor, comprising: a capacitor body including a dielectric layer, a first internal electrode and a second internal electrode alternately disposed with the dielectric layer interposed therebetween, the capacitor body having a first surface and a second surface opposing each other, a third surface and a fourth surface opposing each other and each connected to the first surface and the second surface, and a fifth surface and a sixth surface opposing each other and each connected to the first surface, and the second surface, the third surface and the fourth surface; a first via electrode passing through the first internal electrode and the second internal electrode and exposed through the first surface and the second surface of the capacitor body, the first via electrode being connected to the first internal electrode and being spaced apart from the second internal electrode; a second via electrode passing through the first internal electrode and the second internal electrode and exposed through the first surface and the second surface of the capacitor body, the second via electrode being connected to the second internal electrode and being spaced apart from the first internal electrode; a first external electrode and a second external electrode disposed on the first surface of the capacitor body to be spaced apart from each other and connected to the first via electrode and the second via electrode, respectively; and a first cover and a second cover disposed in sequence from a bottom on the second surface of the capacitor body, wherein the first cover and the second cover are formed of different materials. 2. The multilayer capacitor of claim 1 , wherein the first cover is formed of a ceramic or a dielectric, and the second cover is formed of resin. 3. The multilayer capacitor of claim 2 , wherein the second cover is formed of epoxy resin. 4. The multilayer capacitor of claim 1 , wherein the dielectric layer has a first via through-hole and a second via through-hole formed to allow the first via electrode and the second via electrode to pass therethrough, the first internal electrode includes a first via hole formed in a position corresponding to the first via through-hole and having a size corresponding to the first via through-hole, and a first via spacing hole formed in a position corresponding to the second via through-hole and formed to be larger than the second via through-hole, and the second internal electrode includes a second via hole formed in a position corresponding to the second via through-hole and having a size corresponding to the second via through-hole, and a second via spacing hole formed in a position corresponding to the first via through-hole and formed to be larger than the first via through-hole. 5. The multilayer capacitor of claim 1 , wherein the first internal electrode and the second internal electrode are exposed through the third surface and the fourth surface of the capacitor body, respectively, the multilayer capacitor further comprises a third external electrode and a fourth external electrode disposed on the third surface and the fourth surface of the capacitor body, respectively, and the third external electrode and the fourth external electrode are connected to the first external electrode and the second external electrode, respectively. 6. The multilayer capacitor of claim 1 , wherein the first internal electrode and the second internal electrode are exposed through the third surface and the fourth surface of the capacitor body, respectively, and the first external electrode and the second external electrode are extended onto the third surface and the fourth surface of the capacitor body, respectively. 7. The multilayer capacitor of claim 1 , wherein ends of the first via electrode and the second via electrode are in contact with the first cover. 8. The multilayer capacitor of claim 1 , wherein a thickness of the first cover is in a range from 9 μm to 15 μm, and a thickness of the second cover is in a range from 1 μm to 3 μm. 9. A board having a multilayer capacitor mounted thereon, comprising: a board having a first electrode pad and a second electrode pad disposed to be spaced apart from each other; and the multilayer capacitor according to claim 1 mounted on the board as a first external electrode and a second external electrode are connected to the first electrode pad and the second electrode pad, respectively. 10. The board of claim 9 , wherein the first cover is formed of a ceramic or a dielectric, and the second cover is formed of resin. 11. The board of claim 10 , wherein the second cover is formed of epoxy resin. 12. The board of claim 9 , wherein the dielectric layer has a first via through-hole and a second via through-hole formed to allow the first via electrode and the second via electrode to pass therethrough, the first internal electrode includes a first via hole formed in a position corresponding to the first via through-hole and having a size corresponding to the first via through-hole, and a first via spacing hole formed in a position corresponding to the second via through-hole and formed to be larger than the second via through-hole, and the second internal electrode includes a second via hole formed in a position corresponding to the second via through-hole and having a size corresponding to the second via through-hole, and a second via spacing hole formed in a position corresponding to the first via through-hole and formed to be larger than the first via through-hole. 13. The board of claim 9 , wherein the first internal electrode and the second internal electrode are exposed through the third surface and the fourth surface of the capacitor body, respectively, the multilayer capacitor further comprises a third external electrode and a fourth external electrode disposed on the third surface and the fourth surface of the capacitor body, respectively, and the third external electrode and the fourth external electrode are connected to the first external electrode and the second external electrode, respectively. 14. The board of claim 9 , wherein the first internal electrode and the second internal electrode are exposed through the third surface and the fourth surface of the capacitor body, respectively, and the first external electrode and the second external electrode are extended onto the third surface and the fourth surface of the capacitor body, respectively. 15. The board of claim 9 , wherein ends of the first via electrode and the second via electrode are in contact with the first cover. 16. The board of claim 9 , wherein a thickness of the first cover is in a range from 9 μm to 15 μm, and a thickness of the second cover is in a range from 1 μm to 3 μm.

Assignees

Inventors

Classifications

  • H01G4/242Primary

    the capacitive element surrounding the terminal · CPC title

  • Non-printed capacitor · CPC title

  • Housing; Encapsulation · CPC title

  • for surface mounting, e.g. chip capacitors · CPC title

  • Leadless chip, e.g. chip capacitor or resistor · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10026558B1 cover?
A multilayer capacitor includes a capacitor body including a dielectric layer and a first internal electrode and a second internal electrode; a first via electrode exposed through first and second surfaces of the capacitor body, connected to the first internal electrode and spaced apart from the second internal electrode, a second via electrode exposed through the first and second surfaces of t…
Who is the assignee on this patent?
Samsung Electro Mech
What technology area does this patent fall under?
Primary CPC classification H01G4/242. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).