Magnetic shift register

Patent metadata

Field	Value
Publication number	US-10026431-B2
Application number	US-201415032951-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Nov 1, 2013
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

This disclosure relates to a memory device that includes at least one magnetic track on a substrate, wherein the at least one magnetic track comprises one or more magnetic domains. Contacts can be disposed on the at least one magnetic track according to a predetermined arrangement to form a plurality of bitcells on the at least one magnetic track, wherein each one of the plurality of bitcells is configured to store at least one magnetic domain. The device can include a timing circuit connected to the contacts, with the timing circuit being configured to apply to the contacts multiple phases of electric currents according to a predetermined timing sequence to cause the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track.

First claim

What is claimed is:

1. A memory device, comprising:
at least one magnetic track on a substrate, wherein the at least one magnetic track comprises one or more magnetic domains;
contacts disposed on the at least one magnetic track according to a predetermined arrangement to form a plurality of bitcells on the at least one magnetic track, wherein each one of the plurality of bitcells is configured to store at least one magnetic domain; and
a timing circuit connected to the contacts, with the timing circuit being configured to apply to the contacts multiple phases of electric currents according to a predetermined timing sequence to cause the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track.

2. The memory device of claim 1 , wherein the at least one of the one or more magnetic domains comprises a magnetic domain of a first or a second magnetization as a data bit.

3. The memory device of claim 1 , wherein the contacts disposed on the at least one magnetic track according to the predetermined arrangement comprise contacts disposed along first and second lengths of the at least one magnetic track.

4. The memory device of claim 1 , wherein the contacts disposed on the at least one magnetic track according to the predetermined arrangement comprise contacts disposed along a first length of the at least one magnetic track and not along a second length of the at least one magnetic track.

5. The memory device of claim 1 , wherein the contacts disposed on the at least one magnetic track according to the predetermined arrangement comprises:
a first set of the contacts disposed along a first length of the at least one magnetic track;
a second set of the contacts also disposed along the first length of the at least one magnetic track, wherein the first set of the contacts are spatially interleaved with the second set of the contacts;
a third set of the contacts disposed along a second length of the at least one magnetic track; and
a fourth set of contacts also disposed along the second length of the at least one magnetic track, wherein the third set of the contacts are spatially interleaved with the fourth set of the contacts.

6. The memory device of claim 1 , wherein the contacts disposed on the at least one magnetic track according to the predetermined arrangement comprises:
a first set of the contacts disposed along a first length of the at least one magnetic track and connected to a top side of the at least one magnetic track;
a second set of the contacts disposed along the first length of the at least one magnetic track and connected to a bottom side of the at least one magnetic track, wherein the first set of the contacts are spatially interleaved with the second set of the contacts;
a third set of the contacts disposed along a second length of the at least one magnetic track and connected to the top side of the at least one magnetic track; and
a fourth set of contacts disposed along the second length of the at least one magnetic track and connected to the bottom side of the at least one magnetic track, wherein the third set of the contacts are spatially interleaved with the fourth set of the contacts.

7. The memory device of claim 1 , wherein the contacts disposed on the at least one magnetic track according to the predetermined arrangement comprises:
a first set of the contacts connected to a selected one of a top or bottom side of the at least one magnetic track.

8. The memory device of claim 1 , wherein the each one of the plurality of bitcells comprises a selected set of the contacts, and wherein the timing circuit is configured to apply to the contacts:
first phases of electric currents such that a first pair of the selected set of the contacts is driven to complementary signal levels while a second, different pair of the selected set of the contacts is in a high impedance state; and
second phases of electric currents such that the second pair of the selected set of the contacts is driven to the complementary signal levels while the first pair of the selected set of the contacts is in the high impedance state.

9. The memory device of claim 1 , wherein the magnetic domains are comprised of at least two magnetic domains of opposing first and second magnetizations that are separated by a domain wall.

10. The memory device of claim 1 , wherein at least one of the plurality of bitcells comprises a domain wall separating magnetic domains of opposing first and second magnetizations.

11. The memory device of claim 10 , wherein the domain wall can be moved based on a one of a a) spin-transfer torque principle, b) spin-orbit torque principle, or c) combination of spin-transfer torque principle, and spin-orbit torque principle.

12. The memory device of claim 1 , wherein the each one of the plurality of bitcells comprises a selected set of the contacts and a domain wall, and wherein causing the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track comprises:
applying complementary signal levels to a first pair of the selected set of the contacts to cause a flow of current between the first pair of the selected set of the contacts, the flow of current causing the domain wall to move in a same or an opposite direction relative to the flow of current.

13. The memory device of claim 1 , wherein the each one of the plurality of bitcells comprises a selected set of the contacts and a domain wall, and wherein a movement of the domain wall is at least partially controlled by a back current flowing from one to another of a first pair of the selected set of the contacts driven by complementary signal levels.

14. The memory device of claim 1 , wherein the predetermined arrangement of the contacts along the at least one magnetic track is selected to avoid a flow of current between contacts that are connected to a driver with an output that is in a high impedance state.

15. The memory device of claim 1 , further comprising a read device connected to the at least one magnetic track for detecting a magnetization of a magnetic domain on the at least one magnetic track as a data bit.

16. The memory device of claim 15 , wherein the read device is a selected one of a) a magnetic tunnel junction, and b) a giant magnetoresistive stack.

17. The memory device of claim 1 , further comprising a write device for injecting a domain wall into the at least one magnetic track by causing a current to flow through a wire, wherein the write device comprises the wire disposed adjacent to the at least one magnetic track.

18. The memory device of claim 1 , further comprising a write device for injecting a domain wall into the at least one magnetic track, wherein the write device comprises a magnetic device that is magnetically coupled to a portion of the at least one magnetic track.

19. The memory device of claim 1 , further comprising a write device for injecting a domain wall into the at least one magnetic track, wherein the write device is based on a spin-transfer torque technique.

20. The memory device of claim 1 , wherein the timing circuit comprises a CMOS tri-state drive circuit configured to output at least a logic-1 state and a logic-0 state corresponding to predetermined complementary signal levels, and a high-impedance state corresponding to a floating contact state.

21. A method, comprising:
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Assignees

• Univ Carnegie Mellon

Inventors

• Bromberg David M
• Pileggi Lawrence
• Zhu Jian-Gang

Classifications

• G11B5/746

  Bit Patterned record carriers, wherein each magnetic isolated data island corresponds to a bit · CPC title

• G11B5/743

  Patterned record carriers, wherein the magnetic recording layer is patterned into magnetic isolated data islands, e.g. discrete tracks · CPC title

• G11B5/66

  the record carriers consisting of several layers · CPC title

• G11B5/73921

  Glass or ceramic substrates · CPC title

• G11B5/73911

  Inorganic substrates · CPC title