Dynamic clock lane assignment for increased performance and security

Patent metadata

Field	Value
Publication number	US-10025751-B2
Application number	US-201615061045-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Dec 14, 2015
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

First claim

What is claimed is:

1. A method of dynamically assigning a clock lane in a processor bus comprising a plurality of lanes that communicate signals from a transmitter to a receiver, the method comprising:
sending, with the transmitter, a signal pattern upon each lane,
receiving, with the receiver, the signal pattern upon each lane,
determining, with the receiver, distortion from the received signal pattern associated with each lane,
identifying, with the receiver, a particular lane associated with minimum distortion, and
assigning, with the transmitter, the particular lane associated with minimum distortion as a clock lane that transmits a reference clock signal from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver, wherein the reference clock signal is used to coordinate actions of a first digital circuit within the transmitter and a second digital circuit within the receiver.

2. The method of claim 1 , wherein determining the distortion from the received signal pattern associated with each lane comprises:
generating, with the receiver, an eye diagram associated with each lane from the received signal pattern.

3. The method of claim 2 , wherein identifying the particular lane associated with the minimum distortion comprises:
measuring, with the receiver, an eye width of the eye diagram associated with each lane.

4. The method of claim 3 , wherein identifying the particular lane associated with the minimum distortion further comprises:
identifying the lane associated with the widest eye as the particular lane associated with the minimum distortion.

5. The method of claim 4 , wherein the processor bus comprises an additional lane than is necessary for the bus to communicate a predetermined data width from the transmitter to the receiver.

6. The method of claim 5 , further comprising:
assigning, with the transmitter, the lane associated with the narrowest eye as an inactive lane that does not transmit signals from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver.

7. The method of claim 1 , wherein a first lane within the processor bus is assigned as the particular lane that transmits the clock signal from the transmitter to the receiver at a first transmitter and receiver boot instance and wherein a second lane within the processor bus is assigned as the particular lane that transmits the clock signal from the transmitter to the receiver at a second transmitter and receiver boot instance.

8. A method of dynamically assigning a clock lane in a processor bus comprising a plurality of lanes that communicate signals from a transmitter to a receiver, the method comprising:
assigning, with a transmitter, a first lane of a processor bus as a clock lane that sends a clock signal from the transmitter to the receiver,
iteratively sending, with the transmitter, signal patterns upon each lane of the remaining lanes of the processor bus,
iteratively receiving, with a receiver, the signal patterns upon each lane of the remaining lanes of the processor bus, each iteration increasing a delay step that add time for the receiver to sample the received signal patterns,
iteratively determining, with the receiver, distortions from the iteratively received signal patterns associated with the remaining lanes of the processor bus at each delay step,
assigning, with the transmitter, a second lane of a processor bus as the clock lane that sends the clock signal from the transmitter to the receiver,
repeating the iteratively sending, iteratively receiving, and iteratively determining with the second lane assigned as the clock lane,
identifying, with the receiver, a particular lane associated with a minimum distortion,
determining, with the transmitter, whether the first lane or the second lane was assigned as the clock lane when the particular lane was associated with the minimum distortion,
assigning, with the transmitter, the determined first lane or the second lane as a reference clock lane that transmits the clock signal from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver, wherein the reference clock signal is used to coordinate actions of a first digital circuit within the transmitter and a second digital circuit within the receiver.

9. The method of claim 8 , wherein iteratively determining distortions from the iteratively received signal patterns associated with the remaining lanes of the processor bus at each delay step comprises:
iteratively generating, with the receiver, an eye diagram associated with the remaining lanes of the processor bus from the received signal pattern at each delay step.

10. The method of claim 9 , wherein identifying the particular lane associated with the minimum distortion comprises:
measuring, with the receiver, an eye width of each of the iteratively generated eye diagrams associated with the remaining lanes of the processor bus.

11. The method of claim 10 , wherein identifying the particular lane associated with the minimum distortion further comprises:
identifying the lane associated with the widest eye as the particular lane associated with the minimum distortion.

12. The method of claim 11 , wherein the processor bus comprises an additional lane than is necessary for the bus to communicate a predetermined data width from the transmitter to the receiver.

13. The method of claim 12 , further comprising:
assigning, with the transmitter, the lane associated with the narrowest eye as an inactive lane that does not transmit signals from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver.

Assignees

• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Doyle Matthew S
• Jeanson Mark J
• Maxson Mark O

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4018

  with data-width conversion · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F11/1428

  with loss of hardware functionality · CPC title