System on chip and integrated circuit for performing skew calibration using dual edge and mobile device including the same

Patent metadata

Field	Value
Publication number	US-10025345-B2
Application number	US-201615285633-A
Country	US
Kind code	B2
Filing date	Oct 5, 2016
Priority date	Oct 5, 2015
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

First claim

What is claimed is:

1. A system on chip comprising:
a clock input pin configured to receive an input clock signal;
a data input pin configured to receive an input data signal;
a delay control circuit configured to:
generate first delayed clock signals having different delays, based on a first rising edge of the input clock signal;
generate second delayed clock signals having different delays, based on a first falling edge of the input clock signal;
generate first delayed data signals having different delays, based on a second rising edge of the input data signal; and
generate second delayed data signals having different delays, based on a second falling edge of the input data signal;

a sampling circuit configured to:
perform first sampling on the input data signal, based on the first delayed clock signals, to generate first sampled data signals;
perform second sampling on the first delayed data signals, based on the input clock signal, to generate second sampled data signals;
perform third sampling on the input data signal, based on the second delayed clock signals, to generate third sampled data signals; and
perform fourth sampling on the second delayed data signals, based on the input clock signal, to generate fourth sampled data signals; and

a de-skew control circuit configured to:
compare the first sampled data signals with a first reference signal, and decide a pass or a fail of each of the first sampled data signals, based on the comparison of the first sampled data signals with the first reference signal;
compare the second sampled data signals with a second reference signal, and decide a pass or a fail of each of the second sampled data signals, based on the comparison of the second sampled data signals with the second reference signal;
compare the third sampled data signals with a third reference signal, and decide a pass or a fail of each of the third sampled data signals, based on the comparison of the third sampled data signals with the third reference signal; and
compare the fourth sampled data signals with a fourth reference signal, and decide a pass or a fail of each of the fourth sampled data signals, based on the comparison of the fourth sampled data signals with the fourth reference signal.

2. The system on chip of claim 1 , wherein the de-skew control circuit is further configured to:
generate a first count signal, based on a number of passes decided for the first sampled data signals;
generate a second count signal, based on a number of passes decided for the second sampled data signals;
generate a third count signal, based on a number of passes decided for the third sampled data signals; and
generate a fourth count signal, based on a number of passes decided for the fourth sampled data signals.

3. The system on chip of claim 2 , wherein the de-skew control circuit is further configured to:
transmit, to the delay control circuit, a first delay control signal for controlling a delay of the first rising edge, and transmit, to the delay control circuit, a second delay control signal for controlling a delay of the second rising edge, based on the first count signal and the second count signal; and
transmit, to the delay control circuit, a third delay control signal for controlling a delay of the first falling edge, and transmit, to the delay control circuit, a fourth delay control signal for controlling a delay of the second falling edge, based on the third count signal and the fourth count signal.

4. The system on chip of claim 3 , wherein the delay control circuit is further configured to:
select one of the first delayed clock signals, based on the first delay control signal; and
select one of the second delayed clock signals, based on the third delay control signal.

5. The system on chip of claim 4 , wherein the delay control circuit is further configured to:
select one of the first delayed data signals, based on the second delay control signal; and
select one of the second delayed data signals, based on the fourth delay control signal.

6. The system on chip of claim 1 , wherein the delay control circuit comprises:
a first clock delay circuit configured to generate the first delayed clock signals, based on the first rising edge of the input clock signal;
a second clock delay circuit configured to generate the second delayed clock signals, based on the first falling edge of the input clock signal;
a first data delay circuit configured to generate the first delayed data signals, based on the second rising edge of the input data signal; and
a second data delay circuit configured to generate the second delayed data signals, based on the second falling edge of the input data signal,
the first clock delay circuit is separated from the second clock delay circuit, and
the first data delay circuit is separated from the second data delay circuit.

7. The system on chip of claim 6 , wherein the delay control circuit does not output the first and second delayed clock signals to the sampling circuit at the same time and does not output the first and second delayed data signals to the sampling circuit at the same time.

8. The system on chip of claim 7 , wherein the sampling circuit does not output the first and third sampled data signals at the same time and does not output the second and fourth sampled data signals at the same time.

9. The system on chip of claim 1 , wherein the de-skew control circuit comprises:
a first comparator configured to compare the first sampled data signals with the first reference signal, and decide the pass or the fail of each of the first sampled data signals, based on the comparison of the first sampled data signals with the first reference signal;
a second comparator configured to compare the second sampled data signals with the second reference signal, and decide the pass or the fail of each of the second sampled data signals, based on the comparison of the second sampled data signals with the second reference signal;
a third comparator configured to compare the third sampled data signals with the third reference signal, and decide the pass or the fail of each of the third sampled data signals, based on the comparison of the third sampled data signals with the third reference signal; and
a fourth comparator configured to compare the fourth sampled data signals with the fourth reference signal, and decide the pass or the fail of each of the fourth sampled data signals, based on the comparison of the fourth sampled data signals with the fourth reference signal,
the first comparator is separated from the third comparator, and
the second comparator is separated from the fourth comparator.

10. A mobile system comprising:
a system on chip; and
a data transmitter configured to transmit, to the system on chip, an input data signal and an input clock signal,
wherein the system on chip comprises:
a clock input pin configured to receive the input clock signal;
a data input pin configured to receive the input data signal;
a delay control circuit configured to:
generate first delayed clock signals having different delays, based on a first rising edge of the input clock signal;
generate second delayed clock signals having different delays, based on a first falling edge of the input clock signal;
generate first delayed data signals having different delays, based on a second rising edge of the input data signal; and
generate second delayed data signals having different delays, based on a second falling edge of the input data signal;

a sampling circuit configured to:
perform first sampling on the input data signal, based on the first delayed clock signals, to generate first sampled data signals;
perform second samplin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Phil Jae
• Cha Gyeong Han

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04L7/0041

  Delay of data signal · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title