Method and system for a low parasitic silicon high-speed phase modulator having raised fingers perpendicular to the PN junction

US10025120B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10025120-B2
Application numberUS-201314105527-A
CountryUS
Kind codeB2
Filing dateDec 13, 2013
Priority dateDec 13, 2012
Publication dateJul 17, 2018
Grant dateJul 17, 2018

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Abstract

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Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide, and portions of the p-doped and n-doped regions may be removed. Contacts may be formed on remaining portions of the p-doped and n-doped regions. Portions of the p-doped and n-doped regions may be removed symmetrically about the PN junction waveguide. Portions of the p-doped and n-doped regions may be removed in a staggered fashion along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

First claim

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What is claimed is: 1. A method for a semiconductor device, the method comprising: fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer is on an oxide layer and the oxide layer is on a silicon substrate, said PN junction waveguide having p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides; removing first portions of the p-doped and n-doped regions thereby forming the PN junction waveguide; removing second portions of the p-doped and n-doped regions intermittently along a length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and forming contacts to said fingers of p-doped and n-doped regions. 2. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions symmetrically about the PN junction waveguide. 3. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions in a staggered fashion along the length of the PN junction waveguide. 4. The method according to claim 1 , comprising removing etch transition features along the p-doped and n-doped regions, wherein the etch transition features provide a transition between deep etched and shallow etched features in the optical phase modulator. 5. The method according to claim 1 , wherein the silicon layer, oxide layer, and silicon substrate comprise a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) wafer. 6. The method according to claim 1 , comprising reducing a parasitic capacitance of the optical phase modulator by the removing of the second portions of the p-doped and n-doped regions. 7. The method according to claim 1 , wherein the optical phase modulator is integrated in an optical transceiver formed on the silicon substrate. 8. The method according to claim 1 , wherein the remaining portions of the p-doped and n-doped regions comprise fingers for forming contacts that are staggered on opposite sides along the length of the PN junction waveguide. 9. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions down to the oxide layer on the silicon substrate. 10. The method according to claim 1 , wherein the optical phase modulator is integrated in a Mach-Zehnder interferometer modulator. 11. A system for communication, the system comprising: an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer is on an oxide layer and the oxide layer is on a silicon substrate; first p-doped and n-doped regions on opposite sides along a length forming the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides; regions where the p-doped and n-doped regions have been intermittently removed along the length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and contacts formed on said fingers of p-doped and n-doped regions. 12. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed symmetrically about the PN junction waveguide. 13. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed in a staggered fashion along the length of the PN junction waveguide. 14. The system according to claim 11 , wherein etch transition features are removed along the p-doped and n-doped regions, wherein the etch transition features provide a transition between deep etched and shallow etched features in the optical phase modulator. 15. The system according to claim 14 , wherein the remaining portions of the p-doped and n-doped regions comprise fingers where contacts are formed that are staggered on opposite sides along the length of the PN junction waveguide. 16. The system according to claim 11 , wherein the silicon layer, oxide layer, and silicon substrate comprise a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) wafer. 17. The system according to claim 11 , wherein the optical phase modulator is integrated in an optical transceiver formed on the silicon substrate. 18. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed down to the oxide layer on the silicon substrate. 19. The system according to claim 11 , wherein the optical phase modulator is integrated in a Mach-Zehnder interferometer modulator. 20. A system for communication, the system comprising: a Mach-Zehnder optical modulator that comprises a PN junction waveguide formed in a silicon layer on an oxide layer, wherein the silicon layer and the oxide layer are part of a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) substrate; p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides; regions where the p-doped and n-doped regions have been removed in an alternating fashion along the length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and contacts formed on said fingers of p-doped and n-doped regions.

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Classifications

  • the optical waveguides being made of semiconducting material · CPC title

  • single crystal Si · CPC title

  • integrated waveguide · CPC title

  • G02F1/025Primary

    in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

  • Physics · mapped topic

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What does patent US10025120B2 cover?
Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have p-doped and n-doped regions on opposite sides alon…
Who is the assignee on this patent?
Luxtera Inc, Luxtera Inc
What technology area does this patent fall under?
Primary CPC classification G02F1/025. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).