Data receiving device including an envelope detector and related methods

Patent metadata

Field	Value
Publication number	US-10024888-B2
Application number	US-201715618269-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Dec 30, 2014
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

First claim

What is claimed is:

1. A circuit comprising:
an envelope detector circuit configured to receive a pair of differential signals, the envelope detector circuit comprising:
a first input node configured to receive a first signal of the pair of differential signals,
a second input node configured to receive a second signal of the pair of differential signals,
a reference differential amplifier having a pair of differential inputs configured to receive a pair of fixed voltage signals, the reference differential amplifier configured to be biased with a first bias current,
a data differential amplifier coupled to the first input node and to the second input node, the data differential amplifier configured to be biased with a second bias current, the second bias current being a scaled copy of the first bias current,
a first detector circuit coupled to a first output of the data differential amplifier,
a second detector circuit coupled to a second output of the data differential amplifier; and

a receiver circuit coupled to the envelope detector circuit and configured to generate an output based on an output of the first detector circuit and based on an output of the second detector circuit.

2. The circuit of claim 1 , wherein the pair of differential signals are USB signals.

3. The circuit of claim 1 , further comprising a logic circuit coupled to the output of the first detector circuit and to the output of the second detector circuit, the logic circuit configured to generate a reset signal in a reset node coupled to the receiver circuit.

4. The circuit of claim 1 , further comprising a reference detector circuit coupled to a first current source, the first current source configured to generate the first bias current.

5. The circuit of claim 4 , wherein the first detector circuit and the second detector circuit are replicas of the reference detector circuit.

6. The circuit of claim 1 , wherein the envelope detector circuit further comprises:
a first resistor coupled between the first output of the data differential amplifier and a reference node; and
a second resistor coupled between the second output of the data differential amplifier and the reference node.

7. The circuit of claim 6 , wherein the reference node is coupled to a ground reference.

8. The circuit of claim 6 , wherein the envelope detector circuit further comprises:
a third resistor coupled in series with the first resistor; and
a fourth resistor coupled in series with the second resistor.

9. The circuit of claim 8 , further comprising a first bit detection circuit coupled to the first input node and to the second input node, the first bit detection circuit configured to select a polarity of an output of the receiver circuit based on a first bit.

10. The circuit of claim 9 , wherein the envelope detector circuit further comprises a logic circuit having a first input coupled to a first intermediate node and a second input coupled to a second intermediate node, the first intermediate node coupled between the first resistor and the third resistor, and the second intermediate node coupled between the second resistor and the fourth resistor, wherein the logic circuit is configured to generate a reset signal in a reset node coupled to the receiver circuit.

11. The circuit of claim 1 , wherein the envelope detector circuit further comprises a differential voltage dividing circuit coupled to the first input node and to the second input node, the differential voltage dividing circuit configured to receive the pair of differential signals.

12. A method comprising:
receiving a pair of differential signals with a data differential amplifier biased with a second bias current, the second bias current being a scaled copy of a first bias current used to bias a reference differential amplifier configured to receive a pair of fixed voltage signals;
controlling the first bias current with a reference circuit comprising a reference detector circuit; and
generating an output based on an output of a first detector circuit and based on an output of a second detector circuit, wherein
the first detector circuit is coupled to a first output of the data differential amplifier, and
the second detector circuit is coupled to a second output of the data differential amplifier.

13. The method of claim 12 , wherein the pair of differential signals operate at a speed of 480 Mbps.

14. The method of claim 12 , wherein the first detector circuit and the second detector circuit are replicas of the reference detector circuit.

15. A USB data receiver device comprising:
an envelope detector circuit comprising
first and second inputs configured to receive a differential input signal,
a first detector circuit coupled to the first input, and
a second detector circuit coupled to the second input;

a logic circuit coupled to an output of the first detector circuit and to an output of the second detector circuit, the logic circuit configured to generate a reset signal based upon the first and second detector circuits; and
a receiver circuit coupled to the envelope detector circuit and configured to generate an output based upon an output of the first detector circuit, an output of the second detector circuit, and the reset signal.

16. The USB data receiver device of claim 15 , further comprising a first bit detection circuit coupled to the receiver circuit.

17. The USB data receiver device of claim 15 , wherein the envelope detector circuit further comprises:
a reference differential amplifier having a pair of differential inputs configured to receive a pair of fixed voltage signals, the reference differential amplifier configured to be biased with a first bias current; and
a data differential amplifier coupled to the first input and to the second input, the data differential amplifier configured to be biased with a second bias current, the second bias current being a scaled copy of the first bias current.

18. The USB data receiver device of claim 17 , wherein the envelope detector circuit further comprises a reference detector circuit coupled to a first current source, the first current source configured to generate the first bias current.

19. The USB data receiver device of claim 18 , wherein the first detector circuit and the second detector circuit are replicas of the reference detector circuit.

20. The USB data receiver device of claim 17 , wherein the envelope detector circuit further comprises:
a first resistor coupled between a first output of the data differential amplifier and a reference node; and
a second resistor coupled between a second output of the data differential amplifier and the reference node.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Daljeet
• Nandy Tapas
• Kumar Surendra

Classifications

• G01R19/2503

  for measuring voltage only, e.g. digital volt meters (DVM's) (G01R19/2506 - G01R19/257 take precedence) · CPC title

• G01R19/04 Primary

  Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title