PVT robust closed loop CMOS bias for linear power amplifier

Patent metadata

Field	Value
Publication number	US-10020782-B2
Application number	US-201615286616-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Oct 8, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device may include a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage.

First claim

We claim:

1. A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device comprises:
a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and
a bias control circuit;
wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and
wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage;
wherein each linear power amplifier circuit comprises a cascode amplifier and wherein the replica circuit comprises a replica cascode amplifier that is ideally identical to the cascode amplifier;
wherein the cascode amplifier comprises an input stage amplifier that is serially coupled to an output stage amplifier; wherein the replica cascode amplifier comprises a replica input stage amplifier that is serially coupled to a replica output stage amplifier; wherein the DC voltage bias signals comprises (a) a first DC voltage bias signal that is provided from the replica input stage amplifier to the input stage amplifier and (b) a second bias signal that is provided from the replica output stage amplifier to the output stage amplifier; wherein the input stage amplifier comprises a CMOS input transistor; wherein the output stage amplifier comprises a CMOS output transistor; wherein the replica input stage amplifier comprises a CMOS replica input transistor; and wherein the replica output stage amplifier comprises a CMOS replica output transistor that is coupled between the replica output node and a replica intermediate node.

2. The biasing device according to claim 1 wherein each linear power amplifier circuit comprises a linear power amplifier transistor and wherein the replica circuit comprises a replica transistor that is ideally identical to the linear power amplifier transistor.

3. The biasing device according to claim 1 wherein the biasing control circuit comprises a first control loop for maintaining the replica DC voltage at the fixed value, and a second control loop for maintaining fixed a replica intermediate DC voltage of the replica intermediate node.

4. The biasing device according to claim 3 wherein each one of the first control loop and the second control loop comprises an error amplifier.

5. A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device comprises: a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage wherein the fraction of the replica DC voltage does not exceed 10% of the replica DC voltage.

6. A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device comprises: a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage; wherein the biasing control circuit comprises an error amplifier that is configured to maintain the replica DC voltage fixed at a value that is smaller by the fraction of the replica DC voltage than the linear power amplifier DC voltage; wherein a first input of the error amplifier is coupled to the replica output node and a second input of the error amplifier is coupled to a first input node; wherein the first input node is also coupled to a reference current source; wherein the reference current source is configured to supply the replica DC current.

7. The biasing device according to claim 6 , comprising a first bias control circuit resistor that is configured to set a voltage level of the second input of the error amplifier; and a second bias control circuit resistor that is configured to set the replica DC current.

8. The biasing device according to claim 1 , wherein the biasing device does not take feedback from the linear power amplifier.

9. A method for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the method comprises:
feeding, by a biasing device, a replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; wherein the replica circuit is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; wherein the replica circuit is coupled the multiple linear power amplifier circuits; and
supplying, by the replica circuit, supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or exceeds the replica DC voltage by a fraction of the replica DC voltage;
wherein each linear power amplifier circuit comprises a cascode amplifier and wherein the replica circuit comprises

Assignees

• Dsp Group Ltd

Inventors

• Cohen Avi
• Pongratz Ron

Classifications

• H03F1/301 Primary

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F3/345

  with field-effect devices (H03F3/347 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F1/0216

  Continuous control · CPC title