Method for realizing ultra-thin sensors and electronics with enhanced fragility

Patent metadata

Field	Value
Publication number	US-10020219-B2
Application number	US-201715727195-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Jul 11, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.

First claim

What is claimed is:

1. A method of fabricating ultra-thin semiconductor devices, the method comprising:
forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame;
forming active layers including active devices on upper surfaces of the dielets; and
forming fragility enhancing features in the semiconductor dielets on lower surfaces of the dielets, the fragility enhancing features not extending fully through the dielets to the upper surfaces.

2. The method of claim 1 , wherein forming the fragility enhancing features in the semiconductor dielets includes forming etchings in the semiconductor dielets.

3. The method of claim 1 , wherein the fragility enhancing features are configured to cause the semiconductor dielets to fracture under influence of an external force.

4. The method of claim 1 , wherein the fragility enhancing features are configured to cause the semiconductor dielets to deform and become strained in a manner that degrades electrical performance under influence of an external force.

5. The method of claim 4 , wherein the fragility enhancing features are configured to cause the semiconductor dielets to deform and become strained in a manner that alters carrier mobility in transistors of the semiconductor dielets under the influence of the external force.

6. The method of claim 1 , further comprising etching a notch in the at least one tether.

7. The method of claim 1 , further comprising:
bonding a device wafer including active areas to a carrier wafer, the active areas facing the carrier wafer and aligned with recesses defined in the carrier wafer;
thinning the device wafer; and
etching trenches about the peripheries of the active areas, the trenches defining the at least one tether, boundaries of the semiconductor dielets, and the frame.

8. The method of claim 7 , comprising etching the trenches prior to bonding the device wafer to the carrier wafer.

9. The method of claim 7 , comprising etching the trenches subsequent to thinning the device wafer.

10. The method of claim 7 , wherein thinning the device wafer includes thinning the device wafer to a thickness of about 10 μm.

11. The method of claim 7 , wherein thinning the device wafer includes spin etching a rear side of the device wafer.

12. The method of claim 1 , wherein forming the array of semiconductor dielets includes forming the semiconductor dielets with thicknesses of about 10 μm.

13. The method of claim 1 , wherein forming the array of semiconductor dielets includes forming the semiconductor dielets with spacings of about 10 μm to 50 μm between adjacent semiconductor dielets.

14. The method of claim 1 , further comprising forming electrically conductive traces on the frame and in electrical communication with the semiconductor dielets.

15. The method of claim 1 , further comprising singulating the semiconductor dielets from the frame by mechanically punching the semiconductor dielets from the frame.

16. The method of claim 1 , further comprising singulating the semiconductor dielets from the frame by pulling the semiconductor dielets from the frame using a vacuum pick tool.

17. The method of claim 1 , further comprising singulating the semiconductor dielets from the frame by destroying the at least one tether by laser ablation.

18. A method of fabricating ultra-thin semiconductor devices, the method comprising:
forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame; and
forming fragility enhancing features in the semiconductor dielets, the fragility enhancing features being configured to cause the semiconductor dielets to deform and become strained in a manner that degrades electrical performance under influence of an external force, the external force exacerbating pre-existing inherent strain that exists in fabricated active devices of the semiconductor dielets caused by oxide and/or interlayer dielectric (ILD) and metal routing layers to achieve a strain that causes failure of the semiconductor dielets.

19. A method of fabricating ultra-thin semiconductor devices, the method comprising:
forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame; and
singulating the semiconductor dielets from the frame by destroying the at least one tether with a joule heater integrated into the at least one tether.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Cook Eugene H
• Duwel Amy
• Carter David J
• Perlin Gayatri E

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title