Method and system for scalable, radiation-tolerant, space-rated, high integrity graphics processing unit

Patent metadata

Field	Value
Publication number	US-10019775-B2
Application number	US-201514830951-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Apr 30, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

The provided scalable, radiation tolerant, high-integrity, space-rated Graphical Processing Unit (GPU) supports open interfaces and provides sufficient graphics performance for known display formats as well as as-yet-undefined, futuristic, display formats that may be updated on-mission without needing, for example, a host space vehicle to return to earth or a lunar site. The provided GPU further provides flexibility and dynamic scalability.

First claim

What is claimed is:

1. A method for implementing a graphics processing unit (GPU), comprising:
at a first GPU core:
receiving N input parallel graphic data sets (PGD), each of the N PGD being from a respective one of N graphic sources, where N is a first number;
dynamically creating a first configuration in which each of the N input PGD is coupled to a respective one of N graphics engines;
dynamically (i) enabling P graphics engines, where P is a second number that is less than or equal to N, and (ii) disabling a remaining N-P graphics engines, wherein enabling turns a graphics engine on, and disabling turns a graphics engine off;
at each of the P enabled graphics engines, processing PGD by
(i) determining whether there is data corruption between input PGD to the graphics engine and output PGD from the graphics engine; and
(ii) only when there is no data corruption between input PGD to the graphics engine and output PGD from the graphics engine, (a) generating a validated PGD;
(b) rasterizing the validated PGD, thereby creating a rasterized PGD, and (c) time-synchronizing
the rasterized PGD according to the first configuration, thereby creating a synch-adjusted PGD;

merging the synch-adjusted PGD from each of the P graphics engines, thereby creating merged PGD; and
distributing, according to a first distribution, the merged PGD to a plurality of graphic sinks;

wherein, at each of the P enabled graphics engines, determining whether there is data corruption between input PGD to the graphics engine and output PGD from the graphics engine comprises:
performing a Cyclic Redundancy Check (CRC) on the input PGD based on inserted specialized, non-intrusive, data-independent patterns to determine whether the CRC is valid; and
generating a CRC valid signal and a timestamp signal, when the CRC is determined to be valid; and
wherein time-synchronizing the rasterized PGD comprises processing the CRC valid signal and the timestamp signal.

2. The method of claim 1 , further comprising, at a device configuration module, processing enable signals to generate control signals defining a first distribution, and
wherein the step of merging comprises, at a merge module, receiving synch-adjusted parallel graphical data sets from each of N graphics engines, and the step of distributing comprises deterministically distributing, according to the first distribution, the merged PGD to the plurality of graphic sinks.

3. The method of claim 2 , wherein the first GPU core is one of M GPU cores, and further comprising:
comparing merged PGD from one of the M GPU cores to merged PGD from another of the M cores to determine whether they are equal, which defines a data compare; and
generating an enable signal when there is a data compare, and generating a disable signal when there is not a compare.

4. The method of claim 3 , wherein each of the M GPU cores comprises at least one quality from the set including: radiation tolerant, space-rated, and high integrity.

5. The method of claim 1 , further comprising:
dynamically creating a second configuration in which each of the N input PGD is coupled to one of the N graphics engines, wherein the second configuration is different than the first configuration.

6. The method of claim 1 , further comprising:
deterministically distributing, in real-time, the merged PGD to the plurality of graphic sinks, according to a second distribution, wherein the second distribution is different than the first distribution.

7. A graphics processing unit (GPU), comprising:
a first GPU core, comprising:
N graphic engines, where N is a number;
a source configuration module coupled to N sources of parallel graphic data (PGD), the source configuration module for controlling a configuration defining the input PGD to each graphic engine of the N graphic engines;
the first GPU core to enable P graphics engines, where P is a second number that is less than or equal to N, and disable a remaining N-P graphics engines, wherein enabling turns a graphics engine on, and disabling turns a graphics engine off, wherein
each of the P graphics engine is configured to,
(i) receive input PGD from a respective one of the N sources of PGD in accordance with the source configuration module,
(ii) determine whether there is data corruption between input PGD to the graphics engine and output PGD from the graphics engine, by performing a Cyclic Redundancy Check (CRC) on the input PGD based on inserted specialized, non-intrusive, data-independent patterns to determine whether the CRC is valid, and generating a CRC valid signal and a timestamp signal, when the CRC is determined to be valid;
and
 only when there is no data corruption between input PGD to the graphics engine and output PGD from the graphics engine,
 (a) generate a validated PGD,
 (b) rasterize the validated PGD, thereby creating a rasterized PGD, and
 (c) time-synchronize the rasterized PGD according to the configuration by processing the CRC valid signal and the timestamp signal, thereby creating a synch-adjusted PGD;

a merge module coupled to each of the N graphics engines and configured to (i) receive synch-adjusted PGD, one from each of the P graphic engines, and (ii) merge the P synch-adjusted PGD, generating merged PGD from the first GPU core; and
a distribution module coupled to the merge module and configured to distribute the merged PGD to a plurality of graphic sinks in accordance with a first distribution determined based on enable signals.

8. The GPU of claim 7 , further comprising a graphic data configuration module coupled to the N graphics engines and configured to selectively enable or disable each of the N graphics engines such that the P graphics engines are enabled, defined as turned on, and N-P graphics engines are disabled, defined as turned off.

9. The GPU of claim 8 , wherein the GPU core is further configured to compare the merged PGD from the first core to merged PGD from a second core and (ii) determine whether they are equal, defined as a data compare.

10. The GPU of claim 9 , wherein the GPU core is further configured to generate an enable signal when there is a data compare.

11. The GPU of claim 10 , wherein the first GPU core and the second GPU core are each one of M total cores, and wherein the first GPU core is further configured to compare the merged PGD from the first core to merged PGD from each of the M cores.

Assignees

• Honeywell Int Inc

Inventors

• White Daryl A
• Bonk Ted
• Dang Tu D
• Morgan John Allan

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title