Access-based eviction of blocks from solid state drive cache memory

US10019364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10019364-B2
Application numberUS-201615256463-A
CountryUS
Kind codeB2
Filing dateSep 2, 2016
Priority dateFeb 17, 2015
Publication dateJul 10, 2018
Grant dateJul 10, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memory without reading the corresponding complete segment. The block temperature is based on the frequency of access to the respective block, and a segment temperature is based on the block temperature of its blocks. Additionally, the segment with the lowest segment temperature is selected for eviction from the second memory, and blocks in the selected segment with a block temperature greater than a threshold temperature are identified. The selected segment is evicted, and a segment with the identified blocks is written to the first memory.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: maintaining, in a first memory, a plurality of segments, each segment including a plurality of blocks, and maintaining, in a second memory, a block temperature for each block of each plurality of blocks, wherein the first memory is a read-cache memory where one segment is written at a time, wherein each block is readable from the first memory without reading a corresponding complete segment, a first block temperature of a first block of the blocks being based on a frequency of access of the first block, and a second block temperature of a second block of the blocks assigned to a predefined temperature value responsive to the second block being pinned to a cache, wherein a segment temperature for each respective segment is based on block temperatures for the corresponding plurality of blocks within the respective segment; selecting a segment from the plurality of segments with a lowest segment temperature for eviction based on block temperatures from the second memory; identifying blocks in the selected segment with a block temperature greater than a threshold temperature; evicting the selected segment from the first memory; and writing to the first memory a new segment having the identified blocks. 2. The method as recited in claim 1 , wherein the first block temperature for the first block increases when the first block is accessed, wherein the block temperature for the first block decreases periodically. 3. The method as recited in claim 1 , wherein, for each respective segment, the segment temperature for the respective segement is equal to a total number of bytes in the blocks in the respective segment that have block temperatures greater than or equal to a temperature threshold. 4. The method as recited in claim 1 , wherein each block is associated with a volume, wherein each segment is operable to include blocks from one volume and each segment is operable to include blocks from a plurality of volumes. 5. The method as recited in claim 1 , wherein the read-cache memory is a memory acting as a cache for read requests and not acting as a cache for write requests. 6. The method as recited in claim 1 , wherein the identified blocks are copied forward by being re-cached in the first memory, wherein blocks in the selected segment that were not identified are not copied forward. 7. The method as recited in claim 1 , wherein a non-volatile random-access memory (NVRAM) memory is used as a write cache, wherein the plurality of segments are formed in the NVRAM and transferred to hard disk storage. 8. The method as recited in claim 1 , wherein the blocks of the selected segment are variable sized blocks. 9. The method as recited in claim 1 , wherein the second block temperature of the second block pinned to the cache is assigned to a maximum temperature value. 10. A system comprising: a first memory for storing a plurality of segments, each segment including a plurality of blocks, wherein the first memory is a read-cache memory where one segment is written at a time, wherein each block is readable from the first memory without reading a corresponding complete segment; a second memory for storing a block temperature for each block of each plurality of blocks, a first block temperature of a first block of the blocks being based on a frequency of access of the first block, and a second block temperature of a second block of the blocks assigned to a predefined temperature value responsive to the second block being pinned to a cache, wherein a segment temperature for each respective segment is based on block temperatures for the corresponding plurality of blocks within the respective segment; and a processor to: select a segment from a plurality of segments with a lowest segment temperature for eviction based on block temperatures from the second memory, identify blocks in the selected segment with a block temperature greater than a threshold temperature, evict the selected segment from the first memory, and write a new segment having the identified blocks to the first memory. 11. The system as recited in claim 10 , further comprising: a hard disk storage for keeping all blocks in a non-volatile memory. 12. The system as recited in claim 11 , further comprising: a non-volatile random-access memory (NVRAM) memory used as a write-cache memory, wherein the segments are formed in the NVRAM and transferred to the hard disk storage. 13. The system as recited in claim 10 , wherein blocks are of variable length. 14. The system as recited in claim 10 , wherein a third block temperature of a third block that is cold is assigned another specified temperature value. 15. The system as recited in claim 10 , wherein the second block temperature of the second block pinned to the cache is assigned to a maximum temperature value. 16. The system as recited in claim 10 , wherein, for each respective segment, the segment temperature for the respective segment is based on an amount of data in blocks in the respective segment that have block temperatures greater than or equal to a temperature threshold. 17. The system as recited in claim 10 , wherein the second block temperature of the second block pinned to the cache is unchanged over time. 18. A non-transitory computer-readable storage medium storing computer program instructions that upon execution cause a system to: maintain, in a first memory, a plurality of segments, each segment including a plurality of blocks, and maintain, in a second memory, a block temperature for each block of each plurality of blocks, wherein the first memory is a read-cache memory where one segment is written at a time, wherein each block is readable from the first memory without reading a corresponding complete segment, a first block temperature of a first block of the blocks being based on a frequency of access of the first block, and a second block temperature of a second block of the blocks assigned to a predefined temperature value responsive to the second block being pinned to a cache, wherein a segment temperature for each respective segment is based on block temperatures for the corresponding plurality of blocks within the respective segment; select a segment from the plurality of segments with a lowest segment temperature for eviction based on block temperatures from the second memory; identify blocks in the selected segment with a block temperature greater than a threshold temperature; evict the selected segment from the first memory; and write to the first memory a new segment having the identified blocks. 19. The non-transitory computer-readable storage medium as recited in claim 18 , wherein the second block temperature of the second block pinned to the cache assigned to a maximum temperature value. 20. The non-transitory computer-readable storage medium as recited in claim 18 , wherein, for each respective segment, the segment temperature for the respective segment is based on an amount of data in blocks in the respective segment that have block temperatures greater than or equal to a temperature threshold.

Assignees

Inventors

Classifications

  • Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

  • in relation to throughput · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

  • management of metadata or control data · CPC title

  • for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10019364B2 cover?
Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memo…
Who is the assignee on this patent?
Hewlett Packard Entpr Dev Lp
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).