Cache memory and method of managing the same

Patent metadata

Field	Value
Publication number	US-10019349-B2
Application number	US-201514715683-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Oct 31, 2014
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

First claim

What is claimed is:

1. A method of managing a cache memory, the method comprising:
determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored;
storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, the first address corresponding to only the first region and a second region, the first region being the same size as the first unit data;
storing part of second unit data, among the data to be stored, in the second region of the first address, the second region being the same size as the part of second unit data, wherein the number of bits of the unit data is 3×2 n , where n is a natural number and the number of bits of the data bandwidth is 2 m , where m is a natural number; and
storing remaining second unit data at a second address different from the first address.

2. The method of claim 1 , wherein the remaining second unit data stored at the second address is stored in a same bank as the first unit data stored at the first address and the second address is different from the first address in either a column address or a row address.

3. The method of claim 1 , wherein the remaining second unit data stored at the second address is stored in a bank different from the bank where the first unit data having the first address is stored.

4. The method of claim 3 , wherein the remaining second unit data stored at the second address has a same row address as the bank different from the bank where the first address is stored.

5. The method of claim 1 , wherein, when the remaining second unit data includes cells, the cells are respectively stored at different addresses or in different banks.

6. The method of claim 1 , wherein the data to be stored is at least one selected from among texture data, pixel data, and sensitivity data.

7. The method of claim 1 , wherein the first unit data and the second unit data have different mipmap levels.

8. The method of claim 1 , wherein a mipmap level of the first unit data is lower than a mipmap level of the second unit data.

9. The method of claim 1 , further comprising sequentially storing the data to be stored in the bank on a unit data basis in response to the number of bits of the data bandwidth being the integer multiple of the number of bits of the unit data.

10. A cache memory comprising:
a bank; and
a cache controller configured to store data read from a main memory in the bank,
wherein, in response to a number of bits of a data bandwidth in the bank not being an integer multiple of a number of bits of unit data in the read data, the cache controller stores first unit data, among the read data, in a first region of a first address stored in the bank, the first address corresponding to only a first region and a second region, the first region being the same size as the first unit data, and stores part of second unit data, among the read data, in the second region at the first address, the second region being the same size as the part of second unit data, wherein the number of bits of the unit data is 3×2 n , where n is a natural number, and the number of bits of the data bandwidth is 2 m , where m is a natural number, wherein the cache controller stores remaining second unit data at a second address different from the first address.

11. The cache memory of claim 10 , wherein the remaining second unit data stored at the second address is stored in a same bank as the first unit data stored at the first address and the second address is different from the first address in either a column address or a row address.

12. The cache memory of claim 10 , wherein the remaining second unit data stored at the second address is stored in a bank different from the bank where the first unit data having the first address is stored.

13. The cache memory of claim 12 , wherein the remaining second unit data stored at the second address has a same row address as the bank different from the bank where the first address is stored.

14. The cache memory of claim 10 , wherein, when the remaining second unit data includes cells, the cache controller stores the cells at different addresses or in different banks, respectively.

15. The cache memory of claim 10 , wherein the first unit data and the second unit data have different mipmap levels.

16. The cache memory of claim 10 , wherein a mipmap level of the first unit data is lower than a mipmap level of the second unit data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Seong Hoon
• Seo Woong
• Lee Sang Heon
• Kwon Sun Min
• Kim Ho Young
• Shim Hee Jun

Classifications

• G06F12/0607

  Interleaved addressing · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/1056

  Simplification · CPC title

• G06F12/0207 Primary

  with multidimensional access, e.g. row/column, matrix · CPC title