Time-to-digital system and associated frequency synthesizer

Patent metadata

Field	Value
Publication number	US-10018970-B2
Application number	US-201615244132-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Sep 30, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

First claim

What is claimed is:

1. A time-to-digital system, for receiving a reference clock signal and a variable clock, wherein a frequency of the variable clock is higher than a frequency of the reference clock signal, comprising:
a supplement circuit, for generating a delayed reference clock signal and at least one pulse in response to the variable clock ahead of a transition of the delayed reference clock signal, wherein the delayed reference clock signal is generated according to the reference clock signal and a delay control signal which is determined in response to transitions of the variable clock, wherein the supplement circuit comprises:
a window generation circuit, for generating the delayed reference clock signal and a first window signal according to the delay control signal, wherein the window generation circuit comprises:
a programmable delay circuit, for receiving the delay control signal and accordingly generating a delay count variable, wherein the delay count variable is corresponding to a delay duration; and
a first window generator, coupled to the programmable delay circuit, for generating the delayed reference clock signal by reproducing the reference clock signal after the delay duration; and
a window evaluator, coupled to the programmable delay circuit, for evaluating the first window signal based on the transitions of the variable clock, and accordingly generating the delay control signal; and
a time-to-digital converter (TDC), coupled to the supplement circuit, for receiving the delayed reference clock signal and the at least one pulse in response to the variable clock and accordingly producing a TDC signal.

2. The time-to-digital system according to claim 1 , wherein the delay duration is equivalent to a unit delay times the delay count variable.

3. The time-to-digital system according to claim 2 , wherein the unit delay is shorter than a cycle of the variable clock.

4. The time-to-digital system according to claim 1 , wherein duration of the first window signal is equivalent to the delay duration.

5. The time-to-digital system according to claim 1 , wherein the window evaluator comprises:
an edge counter, coupled to the window generation circuit, for receiving the variable clock and the first window signal, wherein the edge counter starts counting the transitions of the variable clock when the first window signal transits from a first level to a second level, stops counting the transitions of the variable clock when the first window signal transits from the second level to the first level, and accordingly generates a counting value; and
a determination circuit, coupled to the edge counter and the window generation circuit, for generating the delay control signal according to the counting value.

6. The time-to-digital system according to claim 5 , wherein the determination circuit comprises:
a comparator, for comparing the counting value with a threshold value to generate a comparison result.

7. The time-to-digital system according to claim 6 , wherein the threshold value is an odd integer.

8. The time-to-digital system according to claim 7 , wherein the threshold value is 3 or 5.

9. The time-to-digital system according to claim 6 , wherein the determination circuit further comprises:
a step counter, coupled to the comparator and the window generation circuit, for generating the delay control signal if the comparison result indicates a first condition; and
a holding circuit, coupled to the comparator and the window generation circuit, for generating the delay control signal if the comparison result indicates a second condition.

10. The time-to-digital system according to claim 9 , wherein
the step counter generates the delay control signal so that the delay count variable is changed with a step value; and
the holding circuit generates the delay control signal so that the delay count variable remains unchanged.

11. The time-to-digital system according to claim 10 , wherein
the step value is a positive integer if the step counter operates in an up-counting manner; and
the step value is a negative integer if the step counter operates in a down-counting manner.

12. The time-to-digital system according to claim 1 , wherein the supplement circuit comprises:
a pulse trimming circuit, coupled to the time-to-digital converter, for generating the at least one pulse in response to the variable clock according to the variable clock and a first window signal.

13. The time-to-digital system according to claim 12 , wherein the pulse trimming circuit comprises:
a second window generator, for generating a second window signal according to the first window signal and an inversed variable clock, wherein the inversed variable clock is generated according to the variable clock.

14. The time-to-digital system according to claim 13 , wherein duration of the second window signal is shorter than or equivalent to duration of the first window signal.

15. The time-to-digital system according to claim 13 , wherein the pulse trimming circuit further comprises:
a logic gate, coupled to the second window generator and the time-to-digital converter, wherein
the logic gate starts outputting the at least one pulse in response to the variable clock when the second window signal transits from a first level to a second level, and
the logic gate stops outputting the at least one pulse in response to the variable clock to the time-to-digital converter when the second window signal transits from the second level to the first level.

16. A frequency synthesizer, comprising:
a supplement circuit, for receiving a reference clock signal and a variable clock, and generating a delayed reference clock signal and at least one pulse in response to the variable clock ahead of a transition of the delayed reference clock signal, wherein the delayed reference clock signal is generated according to the reference clock signal and a delay control signal which is determined in response to transitions of the variable clock, and a frequency of the variable clock is higher than a frequency of the reference clock signal, wherein the supplement circuit comprises:
a window generation circuit, for generating the delayed reference clock signal and a first window signal according to the delay control signal; and
a window evaluator, coupled to the window generation circuit, for evaluating the first window signal based on a transition of the variable clock, and accordingly generating the delay control signal; and
a time-to-digital converter (TDC), coupled to the supplement circuit, for receiving the delayed reference clock signal and the at least one pulse in response to the variable clock and accordingly producing a TDC signal.

17. The frequency synthesizer according to claim 16 , wherein the supplement circuit comprises:
a pulse trimming circuit, coupled to the time-to-digital converter, for generating the at least one pulse in response to the variable clock and a first window signal.

18. The frequency synthesizer according to claim 16 , further comprising:
an oscillator, coupled to the supplement circuit, for generating the variable clock.

19. A time-to-digital system, for receiving a reference clock signal and a variable clock, wherein a frequency of the variable clock is higher than a frequency of the reference clock signal, comprising:
a supplement circuit, comprising:
a window generation circuit, comprising:
a programmable delay circuit, for receiving a delay control signal and accordingly generating a delay count variable, wherein the window ge

Assignees

• Mediatek Inc

Inventors

• Chuang Yun-Chen
• Lin Ang-Sheng

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title